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| Number | Title | Issue Date |
| 8188564 | Semiconductor device having a planarizing film formed in a region of a step portion A method for manufacturing a semiconductor device including a thin film device unit including a TFT, and a peripheral device unit provided around the thin film device unit and including a semiconductor element, includes a first step of preparing a substrate, a secon... | 05/29/2012 |
| 8159039 | Superjunction device having a dielectric termination and methods for manufacturing the device A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semico... | 04/17/2012 |
| 8129816 | Semiconductor device and method of manufacturing the same A semiconductor device including a semiconductor substrate; an element isolation region formed in the substrate including trenches formed at a first depth and being filled with an element isolation insulating film; an element forming region formed on the substrate a... | 03/06/2012 |
| 8120137 | Isolation trench structure Among structures, methods, devices, and systems for isolation trenches, a semiconductor device is provided that includes a substrate and an isolation trench structure. One such isolation trench structure includes a first isolation trench portion associated with a su... | 02/21/2012 |
| 8120138 | High-Z structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the subs... | 02/21/2012 |
| 8115271 | Reducing device performance drift caused by large spacings between active regions A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active ... | 02/14/2012 |
| 8110891 | Method of increasing deposition rate of silicon dioxide on a catalyst Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The invention provides an aluminum oxide/silicon oxide laminate film formed by sequentially exposing a substrate to ... | 02/07/2012 |
| 8097930 | Semiconductor devices with trench isolations In an embodiment, a semiconductor device is provided. The semiconductor device may include a first diffusion region, a second diffusion region an active region disposed between the first diffusion region and the second diffusion region, a control region disposed abo... | 01/17/2012 |
| 8058700 | Surge overcurrent protection for solid state, smart, highside, high current, power switch An improvement for a smart, highside, high current, power switch module formed in an integrated circuit having at least one composite MOS/FET transistor switch connected to controlling and protection circuits. The power switch module has a load terminal (L), a batte... | 11/15/2011 |
| 8053860 | Semiconductor device and manufacturing method of the same An excessive metallic film on a device isolation region is prevented from contributing to silicidation in an end of a source-drain diffusion layer region to thereby form a silicide film with uniform film thickness. There are sequentially conducted a step of forming ... | 11/08/2011 |
| 8035189 | Semiconductor constructions The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2 being present... | 10/11/2011 |
| 8026571 | Semiconductor-device isolation structure A manufacturing method for a semiconductor-device isolation structure comprises providing a substrate with at least one shallow trench isolation structure, performing a salicide process that forms a recess on the surface of the shallow trench isolation structure, fo... | 09/27/2011 |
| 8013417 | Low cost substrates and method of forming such substrates In one embodiment, the invention provides engineered substrates having a support with surface pits, an intermediate layer of amorphous material arranged on the surface of the support so as to at least partially fill the surface pits, and a top layer arranged on the ... | 09/06/2011 |
| 8008743 | Vapor deposition of silicon dioxide nanolaminates This invention relates to materials and processes for thin film deposition on solid substrates. Silica/alumina nanolaminates were deposited on heated substrates by the reaction of an aluminum-containing compound with a silanol. The nanolaminates have very uniform th... | 08/30/2011 |
| 7994605 | Isolation structure for semiconductor integrated circuit substrate Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to pr... | 08/09/2011 |
| 7989911 | Shallow trench isolation (STI) with trench liner of increased thickness In one embodiment, an integrated circuit includes a substrate having high voltage transistor regions and low voltage transistor regions. The substrate includes a first trench between and adjacent to the high voltage transistor regions, a second trench between and ad... | 08/02/2011 |
| 7956436 | Method of forming a device wafer with recyclable support A method for forming a device wafer with a recyclable support by providing a wafer having first and second surfaces, with at least the first surface of the wafer comprising a semiconductor material that is suitable for receiving or forming electronic devices thereon... | 06/07/2011 |
| 7919828 | Image sensor for reduced dark current A method and structure for reducing dark current in an image sensor includes preventing unwanted electrons from being collected in the photosensitive region of the image sensor. In one embodiment, dark current is reduced by providing a deep n-type region having an n... | 04/05/2011 |
| 7906829 | Semiconductor device having first and second insulation separation regions A semiconductor device includes: a semiconductor substrate having a first surface and a second surface; a first insulation separation region disposed on the first surface of the semiconductor substrate; a second insulation separation region surrounded with the first... | 03/15/2011 |
| 7902628 | Semiconductor device with trench isolation structure The present invention relates to a semiconductor device with a device isolation structure and a method for fabricating the same. The semiconductor device includes: a substrate provided with a trench formed in the substrate; and at least one device isolation structur... | 03/08/2011 |
| 7893519 | Integrated circuit with conductive structures An integrated circuit includes an array of transistors and a number of wordlines, where individual ones of the wordlines are coupled to a number of the transistors in the array. Conductive structures that are insulated from the wordlines are disposed in a layer bene... | 02/22/2011 |
| 7847366 | Well for CMOS imager A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collect... | 12/07/2010 |
| 7834414 | Semiconductor device with tensile strain and compressive strain A semiconductor device according to the present invention includes an active region having a MOS transistor and a groove surrounding the periphery of the active region, in which the groove is filled with a combination of a first material that produces a tensile stra... | 11/16/2010 |
| 7825489 | Semiconductor device and method of producing the same In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns ... | 11/02/2010 |
| 7821097 | Lateral passive device having dual annular electrodes A lateral passive device is disclosed including a dual annular electrode. The annular electrodes form an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, ... | 10/26/2010 |
| 7816758 | Integrated circuit having laterally dielectrically isolated active regions above an electrically contacted buried material, and method for producing the same An integrated circuit is disclosed that includes a first layer made of active semiconductor material and extending along a first side of a buried layer, and trench structures, which cut through the layer made of active semiconductor material and have dielectric wall... | 10/19/2010 |
| 7816759 | Integrated circuit including isolation regions substantially through substrate An integrated circuit including a substrate and trench isolation regions. The substrate supports a device. The trench isolation regions are configured to laterally isolate the device. The trench isolation regions extend substantially through the substrate. ... | 10/19/2010 |
| 7781860 | Semiconductor constructions, and electronic systems The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2 being present... | 08/24/2010 |
| 7777294 | Semiconductor device including a high-breakdown voltage MOS transistor On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain fi... | 08/17/2010 |
| 7772671 | Semiconductor device having an element isolating insulating film A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor... | 08/10/2010 |
| 7755159 | DUV laser annealing and stabilization of SiCOH films A method of fabricating a dielectric film comprising atoms of Si, C, O and H (hereinafter SiCOH) that has improved insulating properties as compared with prior art dielectric films, including prior art SiCOH dielectric films that are not subjected to the inventive d... | 07/13/2010 |
| 7750429 | Self-aligned and extended inter-well isolation structure A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed ... | 07/06/2010 |
| 7750430 | Semiconductor device and method for fabricating the same A method for fabricating a semiconductor device comprises forming a deposition structure including a first substrate, an insulating layer and a second substrate of a SOI substrate; etching the second substrate located in a boundary of cell and core regions and a per... | 07/06/2010 |
| 7745903 | Semiconductor device and a method of manufacturing the same A technique is provided which permits formation within a single chip both a field effect transistor of high reliability capable of suppressing the occurrence of a crystal defect and a field effect transistor of a high integration degree. In a mask ROM section having... | 06/29/2010 |
| 7737526 | Isolated trench MOSFET in epi-less semiconductor sustrate An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This str... | 06/15/2010 |
| 7719078 | Semiconductor device and method of producing the same In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns ... | 05/18/2010 |
| 7701033 | Isolation structures for integrated circuits A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be ... | 04/20/2010 |
| 7696601 | Semiconductor device with SEG film active region A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. Then, a SEG film i... | 04/13/2010 |
| 7649238 | Semiconductor device In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in co... | 01/19/2010 |
| 7626242 | Shallow trench isolation process utilizing differential liners A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce... | 12/01/2009 |
