Class 257/504 - Including means for establishing a depletion region throughout a semiconductor layer for isolating devices in different portions of the layer (e.g., "JFET" isolation)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein means are provided for producing
No. of patents: 58
Last issue date: 09/20/2011

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Number	Title	Issue Date
8022499	Semiconductor memory device including cell isolation structure using inactive transistors Disclosed herein is a semiconductor memory device including floating body cells. The semiconductor memory device includes memory cell active regions formed on a Silicon-On Isolator (SOI) semiconductor substrate, a plurality of floating body cell transistors formed i...	09/20/2011
7944017	Semiconductor device and manufacturing method of the same An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is...	05/17/2011
7701032	Compound semiconductor device A separation element formed of one of a conduction region and a metal layer is placed between two elements in proximity to each other. The separation element is connected to a high resistance element and to a direct current terminal pad. A connection route extending...	04/20/2010
7642617	Integrated circuit with depletion mode JFET An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor up...	01/05/2010
7382015	Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol...	06/03/2008
7339249	Semiconductor device An insulating film is provided in a region surrounding a circuit region on a p type silicon substrate, and a frame-shaped electrode is provided to surround the circuit region on the insulating film. The region directly under the electrode at the surface of the p typ...	03/04/2008
7335952	Semiconductor device and manufacturing method therefor To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method fo...	02/26/2008
7291894	Vertical charge control semiconductor device with low output capacitance In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer...	11/06/2007
7268394	JFET structure for integrated circuit and fabrication method Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alte...	09/11/2007
7253494	Battery mounted integrated circuit device having diffusion layers that prevent cations serving to charge and discharge battery from diffusing into the integrated circuit region The present invention relates to a battery mounted integrated circuit device where an integrated circuit and a solid state battery are formed on the same substrate. In this battery mounted integrated circuit device, a first diffusion layer containing an N-type impur...	08/07/2007
7221010	Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on...	05/22/2007
7196392	Semiconductor structure for isolating integrated circuits of various operation voltages A semiconductor structure includes an isolation ring disposed on a semiconductor substrate, surrounding first and second circuit areas. A buried isolation layer is continuously extended through the first circuit area and the second circuit area, in the semiconductor...	03/27/2007
7170109	Heterojunction semiconductor device with element isolation structure A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are lam...	01/30/2007
7135766	Integrated power devices and signal isolation structure A flip chip power device having an integrated low inductance ground and heat sink path and an isolation structure is provided. A substrate is formed having transistors and an ohmic contact region circumscribing the transistors. Dielectric layers are formed on the su...	11/14/2006
7119393	Transistor having fully-depleted junctions to reduce capacitance and increase radiation immunity in an integrated circuit A floating-gate transistor for an integrated circuit is formed on a p-type substrate. An n-type region is disposed over the p-type substrate. A p-type region is disposed over the n-type region. Spaced apart n-type source and drain regions are disposed in the p-type ...	10/10/2006
7112867	Resistive isolation between a body and a body contact A high resistance region may be used to isolate the body of a first transistor from a body contact. ...	09/26/2006
7071053	Method of forming capacitor with ruthenium top and bottom electrodes by MOCVD A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high i...	07/04/2006
7061069	Semiconductor device having two-layered charge storage electrode A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in...	06/13/2006
7052942	Surface passivation of GaN devices in epitaxial growth chamber The present invention relates to passivation of a gallium nitride (GaN) structure before the GaN structure is removed from an epitaxial growth chamber. The GaN structure includes one or more structural epitaxial layers deposited on a substrate, and the passivation l...	05/30/2006
7038260	Dual gate structure for a FET and method for fabricating same A method for fabricating a dual gate structure for JFETs and MESFETs and the associated devices. Trenches are etched in a semiconductor substrate for fabrication of a gate structure for a JFET or MESFET. A sidewall spacer may be formed on the walls of the trenches t...	05/02/2006
7033961	Epitaxy/substrate release layer The present invention relates to an epitaxial structure having one or more structural epitaxial layers, including a gallium nitride (GaN) layer, which is deposited on a substrate, and a method of growing the epitaxial structure, wherein the structural epitaxial laye...	04/25/2006
6936908	Forward and reverse blocking devices A power device includes a gate electrode, a source electrode, and a drain electrode provided within an active region of a semiconductor substrate of first conductivity type. A vertical diffusion region of second conductivity is provided at a periphery the active reg...	08/30/2005
6927452	Semiconductor device having dual isolation structure and method of fabricating the same In a semiconductor device having a dual isolation structure, and a method of fabricating the same, an epitaxial layer is formed on the entire surface of the semiconductor device. A device region including the semiconductor device and the epitaxial layer is defined b...	08/09/2005
6911687	Buried bit line-field isolation defined active semiconductor areas Active areas of a Dynamic Random Access Memory (DRAM) formed on a semiconductor substrate are defined by buried bit lines on two sides and by conductors separated from the semiconductor substrate by electrically insulating layers on two other sides. The conductors a...	06/28/2005
6894324	Silicon-on-insulator diodes and ESD protection circuits A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at...	05/17/2005
6882024	Semiconductor device having a dummy active region for controlling high density plasma chemical vapor deposition A dummy active region is formed in which abrading processes are averaged. A semiconductor device is characterized in that an active region for forming an actual device, a device separation region being formed by a trench, and a dummy active region formed substantial...	04/19/2005
6847092	Microelectronic capacitor structure with radial current flow A capacitor for a semiconductor device and a method of manufacturing a capacitor for a semiconductor device is disclosed that uses radial current flow. The capacitor includes a semiconductor substrate that includes a plurality of insulation islands. An insulation la...	01/25/2005
6831346	Buried layer substrate isolation in integrated circuits In an embodiment of an integrated circuit structure having buried layer substrate isolation and a method for forming same, a buried layer having conductivity type opposite to that of an overlying well region is used for wells containing transistors prone to noise ge...	12/14/2004
6777722	Method and structure for double dose gate in a JFET A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed af...	08/17/2004
6777753	CMOS devices hardened against total dose radiation effects A CMOS or NMOS device has one or more n-channel FETs disposed on a substrate, the device being resistant to total dose radiation failures, the device further including a negative voltage source, for applying a steady negative back bias to the substrate of the n-chan...	08/17/2004
6633073	Method and apparatus for isolating circuits using deep substrate n-well Techniques to isolate noise-sensitive circuits from noise generated by nearby circuits. In one design, a quiet region is formed on a die when surrounded by a deep n-well formed on top of a p-type substrate. The deep n-well is heavily doped n-type and form...	10/14/2003
6541839	Microelectronics structure comprising a low voltage part provided with protection against a high voltage part and method for obtaining said protection A microelectronic structure with a low voltage part and high voltage part, such that the low voltage part is protected against the high voltage part and process of obtaining this protection. The structure includes at least one low-voltage element (2) and at le...	04/01/2003
6479841	Power component state detector A detector of the state (on or off) of a vertical power component formed in a lightly-doped semiconductor substrate of a first conductivity type having a front surface and a rear surface. The region corresponding to the power component is surrounded with ...	11/12/2002
6380606	Locos isolation process using a layered pad nitride and dry field oxidation stack and semiconductor device employing the same The present invention provides methods of manufacturing a field oxide isolation structure over a semiconductor. One of the methods includes the steps of: (1) depositing a first stack-nitride sublayer over the semiconductor at a first deposition rate and (...	04/30/2002
6329697	Semiconductor device including a charge-dispersing region and fabricating method thereof A semiconductor device and a method of forming thereof include a dummy active region positioned adjacent the device active region. The dummy active region is formed to include an oxide layer of a thickness that is less than the oxide layer of the active r...	12/11/2001
6320217	Semiconductor memory device Conventionally, an insulating film for element isolation has had a uniformly large thickness either in a memory cell area and in a peripheral circuit area so that the total film thickness of the memory cell area having a floating gate electrode, a control...	11/20/2001
6252257	Isolating wall between power components The present invention relates to an isolating wall for separating elementary components formed in different wells, a component located in at least one of the wells being capable of operating with a high current density. The isolating wall exhibits in its ...	06/26/2001
6110804	Method of fabricating a semiconductor device having a floating field conductor A semiconductor device (10) uses a plurality of floating field conductors (26, 28) to provide a substantially uniform electric field along the surface of the drift region (17) of the device (10). This substantially uniform electric field increases the bre...	08/29/2000
6097075	Semiconductor structure for driver circuits with level shifting An arrangement (100) has a low voltage circuit (196') on a first doped well (110) and a high voltage circuit (197') on a second doped well (120) integrated into a common semiconductor substrate (105). The first well (110) laterally extends along a surface...	08/01/2000
6037647	Semiconductor device having an epitaxial substrate and a fabrication process thereof A semiconductor device formed on an epitaxial substrate includes a high-resistance region in the vicinity of an interface between a doped semiconductor substrate and an epitaxial layer thereon. The high-resistance region is advantageously formed by an ion...	03/14/2000

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Class 257/504 - Including means for establishing a depletion region throughout a semiconductor layer for isolating devices in different portions of the layer (e.g., "JFET" isolation)