Class 257/503 - With contact or metallization configuration to reduce parasitic coupling (e.g., separate ground pads for different parts of integrated circuit)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein the chip includes contacts or electrical
No. of patents: 217
Last issue date: 05/22/2012

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Number	Title	Issue Date
8183663	Crack resistant circuit under pad structure and method of manufacturing the same A circuit under pad structure includes a substrate, a pad electrode, wiring layers interlayer insulation layers alternately disposed between the pad electrode and the substrate, and at least one circuit pattern integral with the substrate, disposed beneath the lower...	05/22/2012
8148797	Chip pad resistant to antenna effect and method A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate e...	04/03/2012
7999349	Front-rear contacts of electronics devices with induced defects to increase conductivity thereof An electronic device is proposed. The device is integrated in a chip including at least one stacked layer having a front surface and a rear surface opposite the front surface, the device including: an insulating trench insulating an active region of the chip, the in...	08/16/2011
7994604	Using floating fill metal to reduce power use for proximity communication One embodiment of the present invention provides a system that facilitates reducing the power needed for proximity communication. This system includes an integrated circuit with an array of transmission pads that transmit a signal using proximity communication. A la...	08/09/2011
7982280	Integrated circuits and interconnect structure for integrated circuits An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively. The first source region is arranged between first sides of the first and second dr...	07/19/2011
7923806	Embedded wiring in copper damascene with void suppressing structure A semiconductor device capable of restricting a void growth in a copper wiring. The semiconductor device comprises a semiconductor substrate, an insulation layer formed above the semiconductor substrate, a barrier metal layer that is a first damascene wiring buried ...	04/12/2011
7898056	Seal ring for reducing noise coupling within a system-on-a-chip (SoC) Disclosed is a seal-ring architecture that can minimize noise injection from noisy digital circuits to sensitive analog and/or radio frequency (RF) circuits in system-on-a-chip (SoC) applications. In order to improve the isolation, the seal-ring structure contains c...	03/01/2011
7893518	Method for generating a layout, use of a transistor layout, and semiconductor circuit A method for generating a layout, use of a transistor layout, and semiconductor circuit is provided that includes a matching structure, which has a number of transistors, whose structure is similar to one another, metallization levels with geometrically formed trace...	02/22/2011
7777293	Semiconductor integrated circuit, D-A converter device, and A-D converter device A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper ...	08/17/2010
7589390	Shielded through-via A shielded through-via that reduces the effect of parasitic capacitance between the through-via and surrounding wafer while providing high isolation from neighboring signals. A shield electrode is formed in the insulating region and spaced apart from the through-via...	09/15/2009
7545019	Integrated circuit including logic portion and memory portion An integrated circuit includes a logic portion including M conductive layers, a memory portion including N conductive layers, and at least one common top conductive layer over the logic portion and the memory portion. M is greater than N. ...	06/09/2009
7436040	Method and apparatus for diverting void diffusion in integrated circuit conductors A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a di...	10/14/2008
7405419	Unidirectionally conductive materials for interconnection A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as b...	07/29/2008
7400039	Semiconductor device and semiconductor package For delivering supply power evenly into chip, a semiconductor device includes plural power supply pads 17a and grounding pads 18a, arranged in alternation in X-direction. The device also includes first upper layer power supply wire 17	07/15/2008
7382015	Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol...	06/03/2008
7358560	Flash memory device and method of manufacturing the same A non-volatile memory device includes a semiconductor substrate having an active region defined by isolation films that extend along a first direction. A control gate line extends along in a second direction perpendicular to the first direction. First and second flo...	04/15/2008
7358548	Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner Buffers are arranged in a concentrated manner in a region distant from pads. The region refers to a region in a main region of a semiconductor integrated circuit, except for a central processing unit, a non-volatile memory and a volatile memory. As the buffer requir...	04/15/2008
7352048	Integration of barrier layer and seed layer The present invention generally relates to filling of a feature by depositing a barrier layer, depositing a seed layer over the barrier layer, and depositing a conductive layer over the seed layer. In one embodiment, the seed layer comprises a copper alloy seed laye...	04/01/2008
7344936	Semiconductor wafer with a wiring structure, a semiconductor component, and methods for their production A semiconductor wafer is provided with a wiring structure, and semiconductor chip positions arranged in rows and columns. The semiconductor wafer has at least one coating (6) as a self-supporting dimensionally stable substrate layer (4), and/or as a wi...	03/18/2008
7335964	Semiconductor structures In one aspect, the invention encompasses a semiconductor processing method of forming a material over an uneven surface topology. A substrate having an uneven surface topology is provided. The uneven surface topology comprises a valley between a pair of outwardly pr...	02/26/2008
7334205	Optimization of die placement on wafers A method of optimizing production of semiconductor devices on a wafer comprises steps of characterizing at least one effect of at least one manufacturing component on at least one optimization criterion; inputting user optimization data; and, based on the at least o...	02/19/2008
7329918	Semiconductor memory device including storage nodes and resistors and method of manufacturing the same A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on ...	02/12/2008
7320904	Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the elec...	01/22/2008
7319264	Semiconductor device A semiconductor device has a structure capable of connecting a lead terminal directly to an electrode on a front surface thereof. The semiconductor device includes a first main electrode provided on the front surface, a second main electrode provided on a back surfa...	01/15/2008
7315072	Semiconductor device capable of suppressing current concentration in pad and its manufacture method An interlayer insulating film is formed on a semiconductor substrate. An intra-layer insulating film is formed on the interlayer film. A recess is formed through the intra-layer film. The recess has a pad-part and a wiring-part continuous with the pad-part. The pad-...	01/01/2008
7312511	Semiconductor device with electrically isolated ground structures This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconducto...	12/25/2007
7309622	Integrated circuit package system with heat sink An integrated circuit package system includes providing a substrate. An integrated circuit is attached to the substrate. A plurality of support bars is formed on the substrate. A plurality of adhesive structures is formed. A heat sink is attached to the plurality of...	12/18/2007
7301103	Printed-wiring board, printed-circuit board and electronic apparatus A printed-wiring board having a multiplayer structure including a plurality of insulating layers and a plurality of conducting layers includes a signal pattern provided in at least one of outermost layers of the conducting layers which includes a plurality of pad po...	11/27/2007
7291894	Vertical charge control semiconductor device with low output capacitance In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer...	11/06/2007
7279795	Stacked die semiconductor package In one embodiment, the present invention includes a semiconductor package including a first semiconductor die with first active circuitry and a second semiconductor die with second active circuitry. An intermediate substrate may be located in the package between the...	10/09/2007
7276784	Semiconductor device and a method of assembling a semiconductor device A semiconductor device includes a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members ...	10/02/2007
7273788	Ultra-thin semiconductors bonded on glass substrates A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to...	09/25/2007
7274108	Semiconductor chip capable of implementing wire bonding over active circuits A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure, a metal-metal capacitor formed by at least a pair of metal electrodes on the same plane underneath the bonding...	09/25/2007
7273804	Internally reinforced bond pads Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric structures are substantially reproduced in the metallic bond layer so ...	09/25/2007
7271439	Semiconductor device having pad structure for preventing and buffering stress of silicon nitride film The present invention discloses a semiconductor device having a pad structure for preventing a stress of a silicon nitride film. The semiconductor device includes a semiconductor substrate, a lower structure formed on the semiconductor substrate, a first insulation ...	09/18/2007
7262428	Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the...	08/28/2007
7259573	Surface capacitance sensor system using buried stimulus electrode A surface capacitance sensor system is implemented as an array of sensor electrodes near the surface of the integrated circuit and an array of stimulus electrodes below the sensor electrodes. Rows of stimulus electrodes are driven by sources while the voltages at th...	08/21/2007
7259441	Hollow structure in an integrated circuit and method for producing such a hollow structure in an integrated circuit A pattern of voids in an integrated circuit having a first layer, a first layer surface and adjacent lands on the first layer surface, the adjacent lands enclosing spaces and including a second layer of a first isolation material and a third layer of a second isolat...	08/21/2007
7253487	Integrated circuit chip having a seal ring, a ground ring and a guard ring An integrated circuit chip is provided. The chip includes a silicon substrate, a circuit, a seal ring, a ground ring and a guard ring. The circuit is formed on the silicon substrate and has an input/output (I/O) pad. The seal ring is formed on the silicon substrate ...	08/07/2007
7250353	Method and system of releasing a MEMS structure A MEMs (microelectromechanical systems) structure is provided. In one implementation, the MEMs structure includes a substrate wafer including a MEMs device formed on a surface of the substrate wafer, and a MEMs cover structure to cover the MEMs device formed on the ...	07/31/2007

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Class 257/503 - With contact or metallization configuration to reduce parasitic coupling (e.g., separate ground pads for different parts of integrated circuit)