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| Number | Title | Issue Date |
| 8183662 | Compact semiconductor package with integrated bypass capacitor A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous... | 05/22/2012 |
| 7859079 | Power semiconductor device The present invention relates to a power semiconductor device comprising a switching power semiconductor element, and a free wheeling diode in anti-parallel connection to the switching power semiconductor element. The power semiconductor is characterized in that a r... | 12/28/2010 |
| 7759761 | Semiconductor wafer substrate for power semiconductor components and method for producing the same In a semiconductor wafer substrate (20) for power semiconductor components (1) and in a method for producing the same, the semiconductor wafer substrate (20) has a large-area, buried rear side electrode (3) in form of a layer arranged bet... | 07/20/2010 |
| 7741695 | Semiconductor device Extending from an upper surface of an n− semiconductor layer on a p− semiconductor substrate to the interface between the n− semiconductor layer and the p− semiconductor substrate, a p+ impurity region i... | 06/22/2010 |
| 7683454 | MOS power component with a reduced surface area A MOS power component in which the active regions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. A MOS power transistor according to the present invention alternately includes a source region of a fir... | 03/23/2010 |
| 7535076 | Power semiconductor device The present invention relates to a power semiconductor device comprising a switching power semiconductor element, and a free wheeling diode in anti-parallel connection to the switching power semiconductor element. The power semiconductor is characterized in that a r... | 05/19/2009 |
| 7501689 | Upper-layer metal power standard cell An upper-layer metal power standard cell comprises: a basic power metal layer which is disposed in an upper layer of a circuit and which supplies a power voltage from an outside of the upper-layer metal power standard cell; a transistor element layer which is formed... | 03/10/2009 |
| 7439134 | Method for process integration of non-volatile memory cell transistors with transistors of another type A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method inc... | 10/21/2008 |
| 7405460 | Semiconductor device having a plurality of kinds of wells and manufacturing method thereof A semiconductor device has a configuration in which more than three kinds of wells are formed with small level differences. One kind of well from among the more than three kinds of wells has a surface level higher than other kinds of wells from among the more than t... | 07/29/2008 |
| 7400039 | Semiconductor device and semiconductor package For delivering supply power evenly into chip, a semiconductor device includes plural power supply pads 17a and grounding pads 18a, arranged in alternation in X-direction. The device also includes first upper layer power supply wire 17 | 07/15/2008 |
| 7393770 | Backside method for fabricating semiconductor components with conductive interconnects A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of ... | 07/01/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| 7332788 | Semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it The invention relates to a semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it. In the case of this semiconductor power device, zones (6) in charge compensation cells (27) that ... | 02/19/2008 |
| 7319264 | Semiconductor device A semiconductor device has a structure capable of connecting a lead terminal directly to an electrode on a front surface thereof. The semiconductor device includes a first main electrode provided on the front surface, a second main electrode provided on a back surfa... | 01/15/2008 |
| 7309622 | Integrated circuit package system with heat sink An integrated circuit package system includes providing a substrate. An integrated circuit is attached to the substrate. A plurality of support bars is formed on the substrate. A plurality of adhesive structures is formed. A heat sink is attached to the plurality of... | 12/18/2007 |
| 7304349 | Power semiconductor component with increased robustness The invention relates to a power semiconductor component with increased robustness, in which a contact layer (13, 14) applied directly to a main surface (7, 11) of the semiconductor body (1) is composed of a metal (13) having a high melti... | 12/04/2007 |
| 7294901 | Semiconductor device with improved resurf features including trench isolation structure A p impurity region (3) defines a RESURF isolation region in an n− semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n− | 11/13/2007 |
| 7291894 | Vertical charge control semiconductor device with low output capacitance In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer... | 11/06/2007 |
| 7253492 | Semiconductor structure with via structure A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited... | 08/07/2007 |
| 7244993 | Driving circuit A driving circuit and a data-line driver is provided which are capable of improving the tolerance to noise between adjacent terminals by using a conventional CMOS process while keeping the chip size small, because a high-density N-diffusion layer (116) is pro... | 07/17/2007 |
| 7242076 | Packaged integrated circuit with MLP leadframe and method of making same A packaged integrated circuit having a die with multiple transistors selected from the group consisting of multiple logic, linear and analog linear transistors is provided. The die is attached to a die pad with one or more peripheral leads physically isolated from t... | 07/10/2007 |
| 7238986 | Robust DEMOS transistors and method for making the same Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first p... | 07/03/2007 |
| 7230314 | Semiconductor device and method of forming a semiconductor device A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provid... | 06/12/2007 |
| 7221034 | Semiconductor structure including vias A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited... | 05/22/2007 |
| 7217954 | Silicon carbide semiconductor device and method for fabricating the same An inventive semiconductor device is provided with: a silicon carbide substrate 1; an n-type high resistance layer 2; well regions 3 provided in a surface region of the high resistance layer 2; a p+ contact region 4 prov... | 05/15/2007 |
| 7212036 | Driving apparatus of H bridge circuit and protection method of the same In order to protect semiconductor switching-devices employed in an H bridge circuit against an over-voltage without using a special protection circuit, a control circuit outputs a control signal to a driving circuit for driving the H bridge circuit in order to turn ... | 05/01/2007 |
| 7196393 | Semiconductor device including a high voltage transistor A drain diffusion layer 11b includes a low impurity concentration region 5a and a high impurity concentration region 5b, and the low impurity concentration region 5a is located on the channel region side. An im... | 03/27/2007 |
| 7192810 | Semiconductor packaging An electronic component and a method for making an electronic component are disclosed. The electronic component has a silicon package. The silicon package has a recess formed thereon in which a conductive region is placed. A bare die electronic device is disposed in... | 03/20/2007 |
| 7176578 | Method for processing a thin film substrate The present invention comprises a processed thin film substrate (10) and a method therefore, in order to produce a flexible printed circuit card, having a plurality of microvias going or passing through the thin film substrate and electrically connected along... | 02/13/2007 |
| 7170109 | Heterojunction semiconductor device with element isolation structure A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are lam... | 01/30/2007 |
| 7164200 | Techniques for reducing bowing in power transistor devices Power transistor devices and techniques for reducing bowing in such devices are provided. In one aspect, a power transistor device is provided. The power transistor device comprises a substrate, a device film formed on the substrate and an adhesion layer formed on a... | 01/16/2007 |
| 7154168 | Flip chip in leaded molded package and method of manufacture thereof A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to... | 12/26/2006 |
| 7144764 | Method of manufacturing semiconductor device having trench isolation The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitri... | 12/05/2006 |
| 7126173 | Method for enhancing the electric connection between a power electronic device and its package An electronic power device of improved structure is fabricated with MOS technology to have a gate finger region and corresponding source regions on either sides of the gate region. This device has a first-level metal layer arranged to independently contact the gate ... | 10/24/2006 |
| 7119393 | Transistor having fully-depleted junctions to reduce capacitance and increase radiation immunity in an integrated circuit A floating-gate transistor for an integrated circuit is formed on a p-type substrate. An n-type region is disposed over the p-type substrate. A p-type region is disposed over the n-type region. Spaced apart n-type source and drain regions are disposed in the p-type ... | 10/10/2006 |
| 7115973 | Dual-sided semiconductor device with a resistive element that requires little silicon surface area A dual-sided semiconductor device is formed on a wafer with a resistive element that is formed through the wafer. By forming the resistive element through the wafer, a resistive element, such as a large resistive element, can be formed on the wafer that requires ver... | 10/03/2006 |
| 7084034 | High voltage MOS-gated power device and related manufacturing process MOS-gated power device including a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type. A plurality of doped regions of ... | 08/01/2006 |
| 7071527 | Semiconductor element and manufacturing method thereof A p-channel MOSFET (1) includes a semiconductor substrate (2), an epitaxial region (3), a second diffusion region (6), and a drain region. The epitaxial region (3) is formed on the upper surface of the semiconductor substrate (2... | 07/04/2006 |
| 7067870 | Power semiconductor switching element A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a sourc... | 06/27/2006 |
| 7030426 | Power semiconductor component in the planar technique In a power semiconductor component produced in a planar technique, a near-surface structure having at least one depression is formed in a surface region of an edge termination adjacent a main surface of the semiconductor body. The structure lies inside a space charg... | 04/18/2006 |
