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| Number | Title | Issue Date |
| 8183661 | Semiconductor die with event detection for reduced power consumption According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualif... | 05/22/2012 |
| 8030730 | Semiconductor device and manufacturing method thereof An N-layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N-layer, a trench isolation region is formed to surround the N-layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surfac... | 10/04/2011 |
| 8008742 | Semiconductor memory device and method of fabricating the same Provided are a semiconductor memory device whereby generation of dishing during planarization of a peripheral circuit region is suppressed, and a method of fabricating the semiconductor memory device. The semiconductor memory device includes a semiconductor substrat... | 08/30/2011 |
| 7964933 | Integrated circuit including power diode A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fab... | 06/21/2011 |
| 7944016 | Power managing semiconductor die with event detection circuitry in thick oxide for reduced power consumption According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualif... | 05/17/2011 |
| 7880261 | Isolation technique allowing both very high and low voltage circuits to be fabricated on the same chip An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside... | 02/01/2011 |
| 7880262 | Semiconductor device An active barrier structure has a p-type region and an n-type region, each of which is in contact with a p-type impurity region and which are ohmic-connected to each other to attain a floating potential. A trench isolation structure is formed between an active barri... | 02/01/2011 |
| 7868411 | Semiconductor devices Provided are semiconductor devices and methods of forming the same. In the semiconductor devices and methods of forming the same, different insulating patterns are disposed around a cell gate pattern and a peripheral gate pattern to impose different heat budgets aro... | 01/11/2011 |
| 7829971 | Semiconductor apparatus A semiconductor apparatus is disclosed. The semiconductor apparatus includes an SOI substrate including an active layer, a buried insulation film and a support substrate; a low potential reference circuit part located in the active layer and operable at a first refe... | 11/09/2010 |
| 7763950 | Semiconductor device with multi-trench separation region A semiconductor device is configured that a high-withstand voltage semiconductor device and logic circuits are integrated on a single chip and that a high-withstand voltage high-potential island including the high-potential-side logic circuit is separated using mult... | 07/27/2010 |
| 7714407 | Semiconductor device and method of forming a semiconductor device A high voltage/power semiconductor device has a semiconductor layer having a high voltage terminal end and a low voltage terminal end. A drift region extends between the high and low voltage terminal ends. A dielectric layer is provided above the drift region. An el... | 05/11/2010 |
| 7642616 | Tunnel and gate oxide comprising nitrogen for use with a semiconductor device and a process for forming the device A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor comprising gate oxide and having a wide active area and/or a long channel, and the second transistor typ... | 01/05/2010 |
| 7598589 | Semiconductor device A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first ... | 10/06/2009 |
| 7582946 | Semiconductor device with multi-trench separation region and method for producing the same A semiconductor device is configured that a high-withstand voltage semiconductor device (101) and logic circuits (201 and 301) are integrated on a single chip and that a high-withstand voltage high-potential island (402) including the hig... | 09/01/2009 |
| 7541661 | Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions o... | 06/02/2009 |
| 7521771 | Method for fabricating a semiconductor device A semiconductor device including a semiconductor substrate having first and second device regions. A first trench is formed in the first region and a second trench is formed in the second region. The first trench and the second trench have different widths and diffe... | 04/21/2009 |
| 7453134 | Integrated circuit device with a circuit element formed on an active region having rounded corners An integrated circuit device has a substrate with first and second portions. One or more first active regions are formed in the first portion of the substrate. Each of the one or more first active regions has rounded corners. One or more first circuit elements are f... | 11/18/2008 |
| 7439134 | Method for process integration of non-volatile memory cell transistors with transistors of another type A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method inc... | 10/21/2008 |
| 7439602 | Semiconductor device and its manufacturing method A semiconductor device including memory cells isolated by a trench that may be self aligned with a stacked film pattern (7) has been disclosed. The memory cells may be flash memory cells having an active gate film (2) that may be thinner than a gate ox... | 10/21/2008 |
| 7436023 | High blocking semiconductor component comprising a drift section A semiconductor component having a drift path (2) which is formed in a semiconductor body (1), is composed of a semiconductor material of first conductance type. The drift path (2) is arranged between at least one first and one second electrode ... | 10/14/2008 |
| 7420262 | Electronic component and semiconductor wafer, and method for producing the same The invention relates to an electronic component and a semiconductor wafer, and a method for producing them. The semiconductor wafer has strip-type separating regions. The separating regions are provided with through contacts in the direction of the rear side of the... | 09/02/2008 |
| 7417296 | Dielectric isolation type semiconductor device A dielectric isolation type semiconductor device can achieve high dielectric resistance while preventing the dielectric strength thereof from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A drift N | 08/26/2008 |
| 7416135 | IC tag and IC tag attachment structure A first metal plate for transmission and a second metal plate for transmission are closely-attached to a first surface and a second surface of a dielectric body, respectively. An outer edge of the first metal plate substantially symmetrically faces an outer edge of ... | 08/26/2008 |
| 7394132 | Apparatus and methods for integrated circuit with devices with body contact and devices with electrostatic discharge protection An integrated circuit (IC) includes one or more silicon-on-insulator (SOI) transistors. Each SOI transistor includes a first source region, a second source region, a drain region, a body contact region, a gate, and first and second isolation regions. The body contac... | 07/01/2008 |
| 7391095 | Semiconductor device In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in co... | 06/24/2008 |
| 7388249 | Semiconductor device having self-aligned gate pattern The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a w... | 06/17/2008 |
| 7385274 | High-voltage metal-oxide-semiconductor devices and method of making the same An improved high-voltage process is disclosed. In order to improve the performance in terms of breakdown voltage and to maintain the integrity of the STI structures, the thick gate oxide layer of the high-voltage device area is not etched back before a high-dosage i... | 06/10/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| RE40339 | Silicon-on-insulator chip having an isolation barrier for reliability An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to... | 05/27/2008 |
| 7375409 | Semiconductor device including transistors having different drain breakdown voltages on a single substrate A semiconductor device is provided comprising a supporting substrate, an insulating layer on the substrate, and a first semiconductor layer on the insulating layer. A first high breakdown-voltage transistor is formed in the first semiconductor layer, a second semico... | 05/20/2008 |
| 7364975 | Semiconductor device fabrication methods Methods of fabricating semiconductor devices are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece including a plurality of active area regions defined therein, and forming at least one trench in the ... | 04/29/2008 |
| 7358586 | Silicon-on-insulator wafer having reentrant shape dielectric trenches A bonded SOI wafer and a method for forming a bonded SOI wafer are provided. According to the disclosed method, a first semiconductor wafer is provided, having a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric fil... | 04/15/2008 |
| 7354812 | Multiple-depth STI trenches in integrated circuit fabrication Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider tre... | 04/08/2008 |
| 7355262 | Diffusion topography engineering for high performance CMOS fabrication Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on t... | 04/08/2008 |
| 7339243 | Isolating substrate noise by forming semi-insulating regions An integrated circuit structure for isolating substrate noise and a method of forming the same are provided. In the preferred embodiment of the present invention, a semi-insulating region is formed using proton bombardment in a substrate between a first circuit regi... | 03/04/2008 |
| 7339249 | Semiconductor device An insulating film is provided in a region surrounding a circuit region on a p type silicon substrate, and a frame-shaped electrode is provided to surround the circuit region on the insulating film. The region directly under the electrode at the surface of the p typ... | 03/04/2008 |
| 7339253 | Retrograde trench isolation structures Methods are provided for making retrograde trench isolation structures with improved electrical insulation properties. One method comprises the steps of: forming a retrograde trench in a silicon substrate, and forming a layer of silicon oxide on the walls of the tre... | 03/04/2008 |
| 7332793 | Semiconductor device A transistor region is a region where a plurality of MOS transistors, including an MOS transistor, are formed, and a dummy region is a region lying under a spiral inductor. In the dummy region, a plurality of dummy active layers are disposed in the main surface of a... | 02/19/2008 |
| 7323754 | Semiconductor device and its manufacture method Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the firs... | 01/29/2008 |
| 7320926 | Shallow trench filled with two or more dielectrics for isolation and coupling for stress control A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and fi... | 01/22/2008 |
