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| Number | Title | Issue Date |
| 8124971 | Implementation of diffusion barrier in 3D memory One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding ... | 02/28/2012 |
| 8076673 | Recessed gate dielectric antifuse A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide are formed in the recess and lightly doped source and dra... | 12/13/2011 |
| 7956358 | I-shaped phase change memory cell with thermal isolation A memory device includes two electrodes, vertically separated and having mutually opposed contact surfaces, between which lies a phase change cell. The phase change cell includes an upper phase change member, having a contact surface in electrical contact with the f... | 06/07/2011 |
| 7947980 | Non-volatile memory cell with charge storage element and method of programming An MOS transistor is programmed in a non-volatile memory cell. A storage capacitor in the non-volatile memory cell is used to enhance programming efficiency by providing additional charge to the programming terminal of the MOS transistor during breakdown of the gate... | 05/24/2011 |
| 7910922 | Semiconductor integrated circuit device and manufacture thereof In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for p... | 03/22/2011 |
| 7897967 | Anti-fuse device An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension reg... | 03/01/2011 |
| 7772591 | Electrically-programmable transistor antifuses Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its u... | 08/10/2010 |
| 7714326 | Electrical antifuse with integrated sensor The present invention provides structures for antifuses that utilize electromigration for programming. By providing a portion of antifuse link with high resistance without conducting material and then by inducing electromigration of the conducting material into the ... | 05/11/2010 |
| 7692190 | Semiconductor device The semiconductor device has a fuse and a fuse opening created above the fuse. The fuse is divided into a plurality of lines at a crossing portion where the fuse crosses with an edge of the fuse opening. The plurality of divided lines of the fuse 101 are in p... | 04/06/2010 |
| 7619247 | Structure for amorphous carbon based non-volatile memory A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a second layer of amorphous carbon. The device also includes at least one first conductive layer common to the... | 11/17/2009 |
| 7544968 | Non-volatile memory cell with charge storage element and method of programming An MOS transistor is programmed in a non-volatile memory cell. A storage capacitor in the non-volatile memory cell is used to enhance programming efficiency by providing additional charge to the programming terminal of the MOS transistor during breakdown of the gate... | 06/09/2009 |
| 7470929 | Fuse/anti-fuse structure and methods of making and programming same Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining struc... | 12/30/2008 |
| 7456426 | Fin-type antifuse A method of forming an antifuse forms a material layer and then patterns the material layer into a fin. The center portion of the fin is converted into a substantially non-conductive region and the end portions of the fin into conductors. The process of converting t... | 11/25/2008 |
| 7420204 | Organic transistor An organic transistor is capable of emitting light at high luminescence efficiency, operating at high speed, handling large electric power, and can be manufactured at low cost. The organic transistor includes an organic semiconductor layer between a source electrode... | 09/02/2008 |
| 7372714 | Methods and memory structures using tunnel-junction device as control element A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device... | 05/13/2008 |
| 7373629 | Distributed relocatable voltage regulator An apparatus comprising an integrated circuit having (i) a number of regions each pre-diffused and configured to be metal-programmed and (ii) a plurality of pins configured to connect the integrated circuit to a socket. A logic portion may be implemented on the inte... | 05/13/2008 |
| 7372074 | Surface preparation for selective silicon fusion bonding An apparatus and method for a silicon-based Micro-Electro Mechanical System (MEMS) device, including a pair of silicon cover structures each having a substantially smooth and planar contact surface formed thereon; a silicon mechanism structure having a part thereof ... | 05/13/2008 |
| 7358589 | Amorphous carbon metal-to-metal antifuse with adhesion promoting layers A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting lay... | 04/15/2008 |
| 7358590 | Semiconductor device and driving method thereof A semiconductor device includes a memory with a simple structure, an inexpensive semiconductor device, a manufacturing method and a driving method thereof. One feature is that, in a memory which has a layer including an organic compound as a dielectric, by applying ... | 04/15/2008 |
| 7327629 | Circuit and method for reading an antifuse An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and comp... | 02/05/2008 |
| 7314815 | Manufacturing method of one-time programmable read only memory An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-typ... | 01/01/2008 |
| 7312513 | Antifuse circuit with well bias transistor An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse transistor is coupled to the terminal and includes a first gate terminal coupled to receive a first select signal. ... | 12/25/2007 |
| 7276775 | Intrinsic dual gate oxide MOSFET using a damascene gate process Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an... | 10/02/2007 |
| 7273809 | Method of fabricating a conductive path in a semiconductor device A method for fabricating an ultra-small electrode or plug contact for use in chalcogenide memory cells specifically, and in semiconductor devices generally, in which disposable spacers are utilized to fabricate ultra-small pores into which the electrodes are formed.... | 09/25/2007 |
| 7271440 | Method and apparatus for forming an integrated circuit electrode having a reduced contact area A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A re... | 09/18/2007 |
| 7269898 | Method for making an edge intensive antifuse An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel... | 09/18/2007 |
| 7259427 | Semiconductor device and method of manufacturing the same The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode ... | 08/21/2007 |
| 7256471 | Antifuse element and electrically redundant antifuse array for controlled rupture location An antifuse element (102) having end corners (120, 122) of a gate electrode (104) positioned directly above an active area (106) or bottom electrode. The minimum programming voltage between the gate electrode (104) and the active a... | 08/14/2007 |
| 7256130 | Process for defining a chalcogenide material layer, in particular in a process for manufacturing phase change memory cells A process for defining a chalcogenide material layer using a chlorine based plasma and a mask, wherein the portions of the chalcogenide material layer that are not covered by the mask are etched away. In a phase change memory cell having a stack of a chalcogenide ma... | 08/14/2007 |
| 7253430 | Controllable ovonic phase-change semiconductor memory device An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower... | 08/07/2007 |
| 7247879 | Semiconductor integrated circuit device having particular testing pad arrangement In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for p... | 07/24/2007 |
| 7220670 | Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and products produced by same A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process. ... | 05/22/2007 |
| 7215002 | Electronically programmable antifuse and circuits made therewith An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. ... | 05/08/2007 |
| 7215175 | Fuse sensing scheme with auto current reduction An improved circuit for sensing and programming fuses in integrated circuits. The circuit is broadly comprised of a fuse cell, a reference circuit, a sense amplifier and a level detector. In one embodiment of the present invention, a two-stage sensing scheme is impl... | 05/08/2007 |
| 7211456 | Method for electro-luminescent display fabrication The present invention discloses a method for fabricating a pixel area of an electro-luminescent display device. At least one buffer layer is formed on a substrate. An etch stop layer is formed on the buffer layer. At least one intermediate layer is formed over the e... | 05/01/2007 |
| 7160761 | Vertically stacked field programmable nonvolatile memory and method of fabrication A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus ... | 01/09/2007 |
| 7157782 | Electrically-programmable transistor antifuses Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its u... | 01/02/2007 |
| 7145255 | Lateral programmable polysilicon structure incorporating polysilicon blocking diode A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable s... | 12/05/2006 |
| 7132348 | Low k interconnect dielectric using surface transformation Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely deter... | 11/07/2006 |
| 7130207 | Methods and memory structures using tunnel-junction device as control element A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device... | 10/31/2006 |
