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| Number | Title | Issue Date |
| 8164155 | Semiconductor device and method of manufacturing the same A method for manufacturing a semiconductor device includes forming an N-well and a P-well formed in a semiconductor substrate. An isolation layer may be formed in the semiconductor substrate. At least one dummy active pattern may be formed in a boundary area between... | 04/24/2012 |
| 8110890 | Method of fabricating semiconductor device isolation structure A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or mor... | 02/07/2012 |
| 8039921 | Wiring structure, semiconductor device and manufacturing method thereof A semiconductor device with a high-strength porous modified layer having a pore size of 1 nm or less, which is formed, in a multilayer wiring forming process, by forming a via hole and a wiring trench in a via interlayer insulating film and a wiring interlayer insul... | 10/18/2011 |
| 8035188 | Semiconductor device Plural I/O cells (14) having electrode pads for wire bonding (13) are disposed with spaces (55) between them in the vicinity of a corner of an I/O region (11) of a semiconductor substrate (10), and power supply separation cells ( | 10/11/2011 |
| 8026570 | Semiconductor integrated circuit device having power switch controller with gate insulator thickness for controlling multiple power switches A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a... | 09/27/2011 |
| 8022498 | Electrostatic discharge management apparatus, systems, and methods Apparatus, systems, and methods may include managing electrostatic discharge events by using a semiconductor device having a non-aligned gate to implement a snap-back voltage protection mechanism. Such devices may be formed by doping a semiconductor substrate to for... | 09/20/2011 |
| 8022497 | Semiconductor device comprising insulating film A semiconductor device capable of preventing an interlayer dielectric film from deterioration resulting from a liquid such as a chemical solution penetrating into the interlayer dielectric film and recovering the interlayer dielectric film from deterioration with a ... | 09/20/2011 |
| 8013415 | Semiconductor device having a circular-arc profile on a silicon surface A semiconductor device includes a shallow isolation trench (STI) structure on a silicon substrate for isolating element-forming regions from one another. The surface region of the silicon substrate in the element-forming regions, as viewed in the extending direction... | 09/06/2011 |
| 7999348 | Technique for stable processing of thin/fragile substrates A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer ha... | 08/16/2011 |
| 7982279 | Method of manufacturing stacked-type semiconductor device A method of manufacturing a stacked-type semiconductor device, including the steps of: forming dividing grooves, having a depth corresponding to a finished thickness for a plurality of first chips formed on the face side of a wafer, on the face side of the wafer alo... | 07/19/2011 |
| 7952160 | Packaged voltage regulator and inductor array Inductors packaged with a voltage regulator for an integrated circuit within the same package are deposited to a sufficient thickness to reduce resistance and improve the quality factor. Furthermore, the voltage regulator switches currents through the inductors at a... | 05/31/2011 |
| 7948051 | Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at le... | 05/24/2011 |
| 7902627 | Capacitive isolation circuitry with improved common mode detector An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a su... | 03/08/2011 |
| 7884440 | Semiconductor integrated circuit A semiconductor integrated circuit including digital circuits and analog circuits integrated over a single substrate includes the substrate including portions where the digital circuits and the analog circuits are to be formed, and a plurality of deep-wells formed t... | 02/08/2011 |
| 7884441 | Semiconductor device having polysilicon bit line contact Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a plurality of device isolation layers disposed in a semiconductor substrate, the device isolation layers extending in a word line direction and spaced apart ... | 02/08/2011 |
| 7875953 | Low crosstalk substrate for mixed-signal integrated circuits An integrated circuit laminate with a metal substrate for use with high performance mixed signal integrated circuit applications. The metal substrate provides substantially improved crosstalk isolation, enhanced heat sinking and an easy access to a true low impedanc... | 01/25/2011 |
| 7875952 | Method of transistor level heterogeneous integration and system The present invention relates to a process for fabricating integrated circuit system. More particularly, the process allows for fabrication of highly integrated system-on-a-chip modules through heterogeneous integration of different semiconductor technologies wherei... | 01/25/2011 |
| 7868410 | Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combina... | 01/11/2011 |
| 7843032 | Radio frequency identification device electrostatic discharge management Apparatus, systems, and methods may include managing electrostatic discharge events in radio frequency identification (RFID) devices by using a semiconductor circuit having a non-aligned gate to implement a snap-back voltage protection mechanism. Such circuits may b... | 11/30/2010 |
| 7838959 | Radio frequency (RF) circuit placement in semiconductor devices Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At lea... | 11/23/2010 |
| 7821096 | Semiconductor integrated circuit and system LSI including the same A semiconductor integrated circuit having a diode element includes a diffusion layer which constitutes the anode and two diffusion layers which are provided on the left and right sides of the anode and which constitute the cathode, such that the anode and the cathod... | 10/26/2010 |
| 7791160 | High-performance FET device layout A fast FET, a method and system for designing the fast FET and a design structure of the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source ... | 09/07/2010 |
| 7772670 | Method of simultaneously fabricating isolation structures having rounded and unrounded corners A method facilitates generally simultaneously fabricating a number of shallow trench isolation structures such that some selected ones of the shallow trench isolation structures have rounded corners and other selected ones of the shallow trench isolation structures ... | 08/10/2010 |
| 7737525 | Method for producing low-K CDO films Methods of preparing a carbon doped oxide (CDO) layers having a low dielectric constant are provided. The methods involve, for instance, providing a substrate to a deposition chamber and exposing it to one or multiple carbon-doped oxide precursors having molecules w... | 06/15/2010 |
| 7732889 | Capacitor structure in a semiconductor device A semiconductor device comprises an integrated circuit formed on a substrate with a signal interface and at least one isolator capacitor. The integrated circuit comprises a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on t... | 06/08/2010 |
| 7732888 | Integrated circuit, method for manufacturing an integrated circuit, memory cell array, memory module, and device According to one embodiment of the present invention, a memory cell array comprises a plurality of voids, the spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated... | 06/08/2010 |
| 7714406 | Low-cost electrostatic clamp with fast de-clamp time A method for manufacturing a semiconductor wafer electrostatic clamp, comprising providing a mounting plate, forming an insulative layer on an insulating portion of the mounting plate, forming a first electrode on a first portion of the mounting plate, forming a sec... | 05/11/2010 |
| 7714405 | Layered CU-based electrode for high-dielectric constant oxide thin film-based devices A layered device including a substrate; an adhering layer thereon. An electrical conducting layer such as copper is deposited on the adhering layer and then a barrier layer of an amorphous oxide of TiAl followed by a high dielectric layer are deposited to form one o... | 05/11/2010 |
| 7629666 | Method and structure for implanting bonded substrates for electrical conductivity A partially completed multi-layered substrate, e.g., silicon on silicon. The substrate has a thickness of material from a first substrate. The thickness of material comprises a first face region. The substrate has a second substrate having a second face region. Pref... | 12/08/2009 |
| 7598588 | Semiconductor structure and method of manufacture In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a semiconductor device includes a plurality of rectilinear structures, wherein the plurality of rectilinear structures comprise silicon dio... | 10/06/2009 |
| 7586173 | Method and apparatus for using flex circuit technology to create a reference electrode channel A method of creating a sensor that may include applying a first conductive material on a first portion of a substrate to form a reference electrode and depositing a first mask over the substrate, the first mask having an opening that exposes the reference electrode ... | 09/08/2009 |
| 7579669 | Semiconductor device including power MOS field-effect transistor and driver circuit driving thereof A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and... | 08/25/2009 |
| 7576405 | Semiconductor integrated circuit for reducing leak current through MOS transistors A semiconductor device is composed of: a power control region within which function cells are arranged; a basic power supply line overlapping said power control region, and positioned in a power supply interconnection layer; a virtual power supply line arranged in s... | 08/18/2009 |
| 7564114 | Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming an interface layer, removing a portion of the interface layer, annealing the interf... | 07/21/2009 |
| 7557420 | Low temperature process for polysilazane oxidation/densification Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet... | 07/07/2009 |
| 7557421 | Hybrid radio frequency integrated circuit using gallium nitride epitaxy layers grown on a donor substrate The present invention is a hybrid integrated circuit comprising at least two semiconductor dies. A high performance semiconductor die includes high performance epitaxy layers grown on a donor substrate, which may form active devices such as transistors. A supporting... | 07/07/2009 |
| 7538408 | Inhibition of parasitic transistor operation in semiconductor device A semiconductor device includes a surface layer on the side of a first principal surface of a p-semiconductor substrate, a high side n-isolation-diffused region and a low side n-isolation-diffused region formed apart from each other by a distance that is shorter tha... | 05/26/2009 |
| 7504703 | Semiconductor integrated circuit device A semiconductor integrated circuit device includes a semiconductor substrate having a first surface. First wells of first conductive type are formed on the semiconductor substrate. Second wells of second conductive type are formed on the semiconductor substrate. The... | 03/17/2009 |
| 7485942 | Films deposited at glancing incidence for multilevel metallization Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure that includes a vapor-deposited dielectric material. The dielectric material has a predete... | 02/03/2009 |
| 7476957 | Semiconductor integrated circuit An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of... | 01/13/2009 |
