Class 257/496 - With physical configuration of semiconductor surface to reduce electric field (e.g., reverse bevels, double bevels, stepped mesas, etc.)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein the means to increase breakdown voltage
No. of patents: 136
Last issue date: 11/22/2011

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Number	Title	Issue Date
8063467	Semiconductor structure and method of manufacture In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a first protrusion and a cavity having a boundary that is below a ...	11/22/2011
7915705	SiC semiconductor device having outer periphery structure A SiC semiconductor device includes: a SiC substrate; a SiC drift layer on the substrate having an impurity concentration lower than the substrate; a semiconductor element in a cell region of the drift layer; an outer periphery structure including a RESURF layer in ...	03/29/2011
7800196	Semiconductor structure with an electric field stop layer for improved edge termination capability An exemplary edge termination structure maintains the breakdown voltage of the semiconductor device after it has been sawed off the wafer and packaged by creating an electric field stop layer at a periphery of the semiconductor device. The electric field stop layer ...	09/21/2010
7439595	Field effect transistor having vertical channel structure A first SiO2 thin film, a tungsten gate electrode, and a second SiO2 thin film are selectively formed on a first n+-type GaN contact semiconductor layer in that order and in a multilayer film structure having the three layers, a stri...	10/21/2008
7391094	Semiconductor structure and method of making same A semiconductor structure includes a substrate having a surface and being made of a material that provides atypical surface properties to the surface, a bonding layer on the surface of the substrate, and a further layer molecularly bonded to the bonding layer. A met...	06/24/2008
7361945	Semiconductor device Disclosed herein are a method of manufacturing a semiconductor device, which can prevent a stepped gate from leaning and increase the channel length of the device, thus contributing to an increase in the degree of integration of the device, as well as a semiconducto...	04/22/2008
7358596	Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in...	04/15/2008
7348256	Methods of forming reduced electric field DMOS using self-aligned trench isolation A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon di...	03/25/2008
7335944	High-voltage vertical transistor with a multi-gradient drain doping profile A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being...	02/26/2008
7304363	Interacting current spreader and junction extender to increase the voltage blocked in the off state of a high power semiconductor device A technique of spreading current flowing in a semiconductor device comprising an electrode, a drift region adjacent to the electrode, a junction termination extension implant region in the drift region, and a current spreader adjacent to the junction termination ext...	12/04/2007
7294909	Electronic package repair process A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and th...	11/13/2007
7279757	Double-sided extended drain field effect transistor A double-sided extended drain field effect transistor that includes a gate terminal overlying a channel region in a substrate. The substrate includes a drain region of a first carrier type that is laterally separated from the channel region by a first RESURF region ...	10/09/2007
7268339	Large area semiconductor detector with internal gain A method is provided for forming a semiconductor-detection device that provides internal gain. The method includes forming a plurality of bottom trenches in a bottom surface of an n-doped semiconductor wafer; and forming a second plurality of top trenches in a top s...	09/11/2007
7227242	Structure and method for enhanced performance in semiconductor substrates An etched substrate structure is augmented by conductive material to provide enhanced electrical and/or thermal performance. A semiconductor device substrate comprising active regions defined on a top surface is masked and etched to define a pattern of blind feature...	06/05/2007
7211861	Insulated gate semiconductor device An insulated gate semiconductor device, includes an isolating structure shaped in a circulating section along the periphery of a semiconductor substrate to isolate that part from an inside device region, a peripheral diffusion region of the semiconductor substrate l...	05/01/2007
7199031	Semiconductor system having a pn transition and method for manufacturing a semiconductor system A semiconductor system having a pn transition and a method for manufacturing a semiconductor system are disclosed. The semiconductor system is designed in the form of a chip having an edge region, the semiconductor system includes a first layer of a first conductivi...	04/03/2007
7180152	Process for resurf diffusion for high voltage MOSFET A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0.1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusio...	02/20/2007
7170133	Transistor and method of fabricating the same A transistor and a method of fabricating the same: The transistor includes an isolation layer disposed in a semiconductor substrate to define an active region. A pair of source/drain regions is disposed in the active region, spaced apart from each other. A channel r...	01/30/2007
7154129	Semiconductor arrangement with a p-n transition and method for the production of a semiconductor arrangement A semiconductor system (200), particularly a diode, having a p-n junction is proposed, that is formed as a chip having an edge area, which includes a first layer (2) of a first conductivity type and a second layer (1, 3) of a second conductivity...	12/26/2006
7145214	Substrate for stressed systems and method of making same A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include ...	12/05/2006
7141856	Multi-structured Si-fin Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produc...	11/28/2006
7118942	Method of making atomic integrated circuit device A method of mass-producing a solid state device comprises providing an atomically smooth, solid state material layer no more than 40 Angstroms thick. This layer is uniformly and defect-freely bonded onto a substrate to provide an acceptable device yield. ...	10/10/2006
7105927	Structure of dummy pattern in semiconductor device Disclosed herein is a dummy pattern structure of a semiconductor device. The dummy pattern structure may include daughter dummy patterns respectively formed at places corresponding to vertexes of polygons in regions where metal wirings are not formed in an interlaye...	09/12/2006
7102201	Strained semiconductor device structures Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain regions formed in a body of a semiconductor material and a channel regio...	09/05/2006
7084044	Optoelectronic device and method of manufacture thereof The present invention provides an optoelectronic device and a method of manufacture thereof. In one embodiment, the method of manufacturing the optoelectronic device may include creating a multilayered optical substrate and then forming a self aligned dual mask over...	08/01/2006
7049206	Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in...	05/23/2006
7030426	Power semiconductor component in the planar technique In a power semiconductor component produced in a planar technique, a near-surface structure having at least one depression is formed in a surface region of an edge termination adjacent a main surface of the semiconductor body. The structure lies inside a space charg...	04/18/2006
7026650	Multiple floating guard ring edge termination for silicon carbide devices Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on t...	04/11/2006
7011991	Method of making atomic integrated circuit device A method of mass-producing a solid state device comprises providing an atomically smooth, solid state material layer no more than 40 Angstroms thick. This layer is uniformly and defect-freely bonded onto a substrate to provide an acceptable device yield. ...	03/14/2006
7009270	Substrate for stressed systems and method of making same A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include ...	03/07/2006
6992350	High voltage power MOSFET having low on-resistance A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region betwee...	01/31/2006
6972477	Circuit device with conductive patterns separated by insulating resin-filled grooves To make thin a circuit device 10 in which are incorporated a plurality of types of circuit elements 12 that differ in thickness, first conductive patterns, onto which comparatively thin circuit elements 12A are mounted, are formed thickly, and s...	12/06/2005
6930011	Semiconductor device with a bipolar transistor, and method of manufacturing such a device A semiconductor device includes a preferably discrete bipolar transistor with a collector region, a base region, and an emitter region which are provided with connection conductors. A known means of preventing a saturation of the transistor is that the latter is pro...	08/16/2005
6919598	LDMOS transistor with enhanced termination region for high breakdown voltage with low on-resistance A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A...	07/19/2005
6909142	Semiconductor device including a channel stop structure and method of manufacturing the same It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surf...	06/21/2005
6900523	Termination structure for MOSgated power devices The termination of a MOSgated device is formed by a trench bevel which surrounds the active device area. The trench bevel has flat walls which extend into and through the epitaxial layer containing the active area which has a lateral extend equal to or less than the...	05/31/2005
6885084	Semiconductor transistor having a stressed channel A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium....	04/26/2005
6855986	Termination structure for trench DMOS device and method of making the same Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In ...	02/15/2005
6818945	Semiconductor device A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate of a first conductive type; a semiconductor layer of the first conductive type formed on the semiconductor substrate; a base layer of a second conductive ...	11/16/2004
6744112	Multiple chip guard rings for integrated circuit and chip guard ring interconnect An integrated circuit having structure for isolating circuit sections having at least one differing characteristic. The structure includes a chip guard ring for each circuit section having the at least one differing characteristic. Providing multiple chip guard ring...	06/01/2004

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Class 257/496 - With physical configuration of semiconductor surface to reduce electric field (e.g., reverse bevels, double bevels, stepped mesas, etc.)