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| Number | Title | Issue Date |
| 8138569 | Guard ring structures and method of fabricating thereof A guard ring structure for use in a semiconductor device. The guard ring structure includes a semiconductor layer stack having a first layer and a second layer on top of the first layer, gates structures formed in the first layer; and guard rings formed in the first... | 03/20/2012 |
| 8093676 | Semiconductor component including an edge termination having a trench and method for producing A semiconductor component includes a semiconductor body having a first side, a second side, an edge delimiting the semiconductor body in a lateral direction, an inner region and an edge region. A first semiconductor zone of a first conduction type is arranged in the... | 01/10/2012 |
| 8018022 | Guard ring structures and method of fabricating thereof A guard ring structure for use in a semiconductor device. The guard ring structure includes a semiconductor layer stack having a first layer and a second layer on top of the first layer, gates structures formed in the first layer; and guard rings formed in the first... | 09/13/2011 |
| 7868409 | Semiconductor integrated circuit with solder bump A semiconductor integrated circuit which is connected to a substrate by solder bumps wherein, when at least one solder bump is connected to a signal line of the semiconductor integrated circuit and the semiconductor integrated circuit is mounted on the substrate, th... | 01/11/2011 |
| 7825487 | Guard ring structures and method of fabricating thereof A guard ring structure for use in a semiconductor device. The guard ring structure includes a semiconductor layer stack having a first layer and a second layer on top of the first layer, gates structures formed in the first layer; and guard rings formed in the first... | 11/02/2010 |
| 7436040 | Method and apparatus for diverting void diffusion in integrated circuit conductors A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a di... | 10/14/2008 |
| 7427795 | Drain-extended MOS transistors and methods for making the same Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) ov... | 09/23/2008 |
| 7391083 | Semiconductor device and a method of manufacturing the same A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger... | 06/24/2008 |
| 7385273 | Power semiconductor device A power semiconductor device that includes a plurality of gate structure each having a gate insulation of a first thickness, and a termination region, the termination including a field insulation body surrounding the active region and having a recess that includes a... | 06/10/2008 |
| 7375408 | Fabricating method of a high voltage metal oxide semiconductor device A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped regio... | 05/20/2008 |
| 7361965 | Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the... | 04/22/2008 |
| 7361957 | Device for electrostatic discharge protection and method of manufacturing the same The present invention relates to a device for electrostatic discharge protection (ESD). According to an embodiment of the present invention, a device for electrostatic discharge protection includes a semiconductor substrate, a plurality of field oxide films formed i... | 04/22/2008 |
| 7355257 | Semiconductor superjunction device A semiconductor superjunction device has a superjunction structure formed in a drift region of the device. The superjunction structure has alternately arranged n-type regions and p-type semiconductor regions layered parallel with the drift direction of carriers, per... | 04/08/2008 |
| 7348256 | Methods of forming reduced electric field DMOS using self-aligned trench isolation A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon di... | 03/25/2008 |
| 7339236 | Semiconductor device, driver circuit and manufacturing method of semiconductor device The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS tr... | 03/04/2008 |
| 7327007 | Semiconductor device with high breakdown voltage A technique is provided which allows easy achievement of a semiconductor device with desired breakdown voltage. In a high-potential island region defined by a p impurity region, an n+ impurity region is formed in an n− semiconductor layer, an... | 02/05/2008 |
| 7307330 | Reverse blocking semiconductor device and a method for manufacturing the same A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, w... | 12/11/2007 |
| 7301179 | Semiconductor device having a high breakdown voltage transistor formed thereon An ion-through region 100, 102 is provided as a first opening in a passivation film 90 on a source electrode 70 and a drain electrode 80. The passivation film 90 is coated with a sealing resin to package the semiconductor device. A... | 11/27/2007 |
| 7285837 | Electrostatic discharge device integrated with pad A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. F... | 10/23/2007 |
| 7282780 | Semiconductor device A capacitor having low voltage dependency and high pn junction diode reverse breakdown voltage. A first n-well is formed in the surface of a p-type silicon substrate. A second n-well is superimposed and formed in the first n-well. A gate electrode is formed along th... | 10/16/2007 |
| 7279768 | Semiconductor device for overvoltage protection In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across an upper surface of the N-type buried diffusion layer over a wide range to form... | 10/09/2007 |
| 7279745 | Semiconductor device In a semiconductor device of the present invention, an N-type epitaxial layer 2 is deposited on a P-type substrate 1. In the epitaxial layer 2, a P-type diffusion layer 5 to be used as a back gate region is formed. An N-type diffusion lay... | 10/09/2007 |
| 7250660 | ESD protection that supports LVDS and OCT Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In t... | 07/31/2007 |
| 7242055 | Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide A semiconductor structure is provided that includes a Vt stabilization layer between a gate dielectric and a gate electrode. The Vt stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a target... | 07/10/2007 |
| 7238987 | Lateral semiconductor device and method for producing the same A high withstand voltage lateral semiconductor device capable of improving its on-state breakdown voltage and safe operation area (SOA) without lowering its current capabilities, and structured so as to be easy to produce. The lateral semiconductor device comprises ... | 07/03/2007 |
| 7189610 | Semiconductor diode and method therefor In one embodiment, a diode is formed with anodes on two surfaces of a semiconductor substrate. ... | 03/13/2007 |
| 7183626 | Passivation structure with voltage equalizing loops A semiconductor device which includes a passivation structure formed with a conductive strip of resistive material that crosses itself once around the active region of the device to form a first closed loop, a continuous strip that loops around the first closed loop... | 02/27/2007 |
| 7180152 | Process for resurf diffusion for high voltage MOSFET A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0.1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusio... | 02/20/2007 |
| 7178126 | Method of protecting a semiconductor integrated circuit from plasma damage In the design of an integrated circuit having a semiconductor substrate and metal interconnecting lines, including a core ring with metal power and ground lines that supply power to a core area inside the core ring, one or more metal-oxide-semiconductor capacitor un... | 02/13/2007 |
| 7154150 | Low triggering N MOS transistor for ESD protection working under fully silicided process without silicide blocks An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+/n−/p−/n−/n+ regions. The emitter is formed of the second N+ region and the second N− well. The pa... | 12/26/2006 |
| 7148731 | Duty cycle correction A duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal havin... | 12/12/2006 |
| 7138698 | Semiconductor device including power MOS field-effect transistor and driver circuit driving thereof A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and... | 11/21/2006 |
| 7135751 | High breakdown voltage junction terminating structure A high breakdown voltage junction terminating structure having a loop-like RESURF structure formed on a SOI substrate is disclosed. A lateral IGBT, a lateral FWD, an output stage element and a driving circuit are formed in the inside region of the structure. The lat... | 11/14/2006 |
| 7114140 | Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system Repeater cells each comprising a buffer or an inverter and an n+ diffusion layer-P well type protection diode or a p+ diffusion layer-N well type antenna protection diode connected to an input pin of the buffer or the inverter for preventing antenna damage or an ant... | 09/26/2006 |
| 7109562 | High voltage laterally double-diffused metal oxide semiconductor A high voltage laterally double-diffused metal oxide semiconductor (LDMOS) stricture is characterized as follows: the second source electrode metal layer connected to the first source electrode metal layer protrudes out of a certain length relative to the first sour... | 09/19/2006 |
| 7067376 | High voltage power MOSFET having low on-resistance A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region betwee... | 06/27/2006 |
| 7060562 | Method for fabricating gate electrodes in a field plate trench transistor, and field plate trench transistor A method for fabricating gate electrodes (7) in a field plate trench transistor (1) having a cell array with a plurality of trenches (3) and a plurality of mesa regions (8) arranged between the trenches comprises the following steps: appl... | 06/13/2006 |
| 7053453 | Substrate contact and method of forming the same A substrate contact and semiconductor chip, and methods of forming the same. The substrate contact is employable with a semiconductor chip formed from a semiconductor substrate and includes a seal ring region about a periphery of an integrated circuit region. In one... | 05/30/2006 |
| 7049674 | Reverse blocking semiconductor device and a method for manufacturing the same A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, w... | 05/23/2006 |
| 7023050 | Super junction / resurf LDMOST (SJR-LDMOST) A lateral double diffused MOSFET (LDMOST) incorporates both the reduced surface field (RESURF) and super junction (SJ) in a split-drift region to significantly improve the on-state, off-state and switching characteristics in junction-isolated (JI) technology. The st... | 04/04/2006 |
