Class 257/413 - Polysilicon laminated with silicide

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein the refractory material is a laminate
No. of patents: 473
Last issue date: 04/24/2012

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Number	Title	Issue Date
8164146	Substrate symmetrical silicide source/drain surrounding gate transistor Field effect transistors described herein include first and second terminals vertically separated by a channel region. The first and second terminals comprise first and second silicide elements respectively. The first silicide element prevents the migration of carri...	04/24/2012
8076736	Semiconductor device and method for manufacturing the same A semiconductor device according to the present invention comprises a silicon carbide semiconductor substrate (1) including a silicon carbide layer (2); a high-concentration impurity region (4) provided in the silicon carbide layer (2); a...	12/13/2011
7968957	Transistor gate electrode having conductor material layer Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor mate...	06/28/2011
7964923	Structure and method of creating entirely self-aligned metallic contacts The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a...	06/21/2011
7948040	Semiconductor device A semiconductor device includes a semiconductor layer overlapping with a gate electrode and having an impurity region outside a region which overlaps with the gate electrode; a first conductive layer which is provided on a side provided with the gate electrode of th...	05/24/2011
7928519	Method for manufacturing capacitive sensor, and capacitive sensor In the method for manufacturing a capacitance sensor according to the present invention, after a protection layer is pattern-formed on the surface of a silicon substrate, a first metal layer is formed on the surface of a silicon substrate so as to be opposed to a pr...	04/19/2011
7825482	Semiconductor device and method for fabricating the same A semiconductor device includes: an isolation region formed in a semiconductor substrate; a first active region and a second active region surrounded by the isolation region; an n-type gate electrode and a p-type gate electrode formed on gate insulating films; an in...	11/02/2010
7745890	Hybrid metal fully silicided (FUSI) gate A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal la...	06/29/2010
7737512	Integrated circuit devices having uniform silicide junctions Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes...	06/15/2010
7732880	Semiconductor device and method of manufacturing the same A conventional semiconductor device, for example, a MOS transistor including an offset gate structure has a problem that it is difficult to reduce the device size. In a semiconductor device according to the present invention, for example, in a P-channel MOS transist...	06/08/2010
7709911	Semiconductor device having silicide transistors and non-silicide transistors formed on the same substrate and method for fabricating the same A semiconductor device includes a first MIS transistor of a non-salicide structure and a second MIS transistor of a salicide structure which are both formed on a substrate of silicon. The first MIS transistor includes a first gate electrode of silicon, first sidewal...	05/04/2010
7642610	Transistor gate electrode having conductor material layer Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor mate...	01/05/2010
7615831	Structure and method for fabricating self-aligned metal contacts A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal...	11/10/2009
7602031	Method of fabricating semiconductor device, and semiconductor device Disclosed is a method of fabricating a semiconductor device that includes field effect transistors each having a gate electrode formed only of a metal silicide which overcomes the problem of depletion of the gate and makes adjustment of a work function easier, and t...	10/13/2009
7545009	Word lines for memory cells Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory m...	06/09/2009
7427546	Transistor device and method for manufacturing the same A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate insulation layer is formed, and source and drain regions located ove...	09/23/2008
7413955	Transistor for memory device and method for manufacturing the same Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a gro...	08/19/2008
7411258	Cobalt disilicide structure A structure relating to removal of an oxide of titanium generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The structure may comprise a layer of cobalt disilicide that is substantially free of c...	08/12/2008
7408190	Thin film transistor and method of forming the same A thin film transistor including a gate, a gate insulating layer, a semiconductor layer and a source/drain is provided. The gate is disposed over a substrate, wherein the gate comprises at least one molybdenum-niobium alloy nitride layer. The gate insulating layer i...	08/05/2008
7405450	Semiconductor devices having high conductivity gate electrodes with conductive line patterns thereon Semiconductor devices that include a semiconductor substrate and a gate line are provided. The gate line is on the semiconductor substrate and includes a gate insulation pattern and a gate electrode which are stacked on the substrate in the order named. A spacer is ...	07/29/2008
7402863	Trench FET with reduced mesa width and source contact inside active trench A trench FET has source contacts which contact the entire top surface of source regions, and contact a portion of side walls of the source regions. The side walls of the source regions form a portion of the side walls of the trenches in the trench FET. ...	07/22/2008
7382028	Method for forming silicide and semiconductor device formed thereby A method for forming silicide and a semiconductor device formed thereby. A Si-containing polycrystalline region is converted to an amorphous region, and annealed to form a regrown polycrystalline region having an increased grain size. A silicide layer is formed by r...	06/03/2008
7378336	Split poly-SiGe/poly-Si alloy gate stack A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer o...	05/27/2008
7365400	Semiconductor device and method for manufacturing the same A method for manufacturing semiconductor device employs an EXTIGATE structure. In accordance with the method, a predetermined thickness of the device isolation film is etched to form a recess. The recess is then filled with a second nitride film. A stacked structure...	04/29/2008
7365403	Semiconductor topography including a thin oxide-nitride stack and method for making the same A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes grow...	04/29/2008
7365404	Semiconductor device having silicide reaction blocking region A semiconductor device has a silicon substrate, an n-type well region formed in the silicon substrate, first and second source/drain regions constructed of a p-type diffusion layer formed on the n-type well region, a gate insulator formed in a region located between...	04/29/2008
7361565	Method of forming a metal gate in a semiconductor device In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is po...	04/22/2008
7361932	Semiconductor device and method for fabricating the same A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a...	04/22/2008
7354847	Method of trimming technology A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature havi...	04/08/2008
7341916	Self-aligned nanometer-level transistor defined without lithography A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates form...	03/11/2008
7332420	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semicon...	02/19/2008
7332421	Method of fabricating gate electrode of semiconductor device A method of forming a gate electrode of a semiconductor device includes forming a damascene pattern for fabricating a metal electrode on an upper part of a poly silicon gate so as to prevent a metal electrode from being oxidized when the poly silicon electrode and t...	02/19/2008
7332388	Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same A method for forming transistor gates having two different work functions comprises forming a first polysilicon layer which may be doped with n-type dopants. The first polysilicon layer comprises an inhibitor material at select locations which retards silicide forma...	02/19/2008
7323419	Method of fabricating semiconductor device A method of fabricating a semiconductor device including a high-k dielectric for as a gate insulating layer is provided. The method includes forming a high-k dielectric layer and a conductive layer on a substrate, dry etching a portion of the conductive layer, perfo...	01/29/2008
7320919	Method for fabricating semiconductor device with metal-polycide gate and recessed channel A method for fabricating a semiconductor device with a metal-polycide gate and a recessed channel, including the steps of: forming trenches for a recessed channel in an active area of a semiconductor substrate; forming a gate insulating layer on the semiconductor su...	01/22/2008
7312504	Transistor for memory device and method for manufacturing the same Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a gro...	12/25/2007
7309901	Field effect transistors (FETs) with multiple and/or staircase silicide A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical conta...	12/18/2007
7307871	SRAM cell design with high resistor CMOS gate structure for soft error rate improvement A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through ...	12/11/2007
7294893	Titanium silicide boride gate electrode A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the ...	11/13/2007
7294890	Fully salicided (FUSA) MOSFET structure A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI reg...	11/13/2007

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Class 257/413 - Polysilicon laminated with silicide