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A self defense weapon formed as a memo pad and which is easily held by a person's fingers, therefore making it possible to provide protection from a mugger and also to quickly and easily write a record or a message without failure of missing or forgetting significant information under a stressful situation.
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| Number | Title | Issue Date |
| 8148788 | Semiconductor device and method of manufacturing the same The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semicond... | 04/03/2012 |
| 8143679 | Termination structure for power devices A semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. The termination region includes a first silicon regio... | 03/27/2012 |
| 8143680 | Gated diode with non-planar source region A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed ... | 03/27/2012 |
| 8097925 | Integrated circuit guard rings Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may ... | 01/17/2012 |
| 8072035 | Semiconductor device and method of manufacturing the same In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high volta... | 12/06/2011 |
| 8074197 | Shielding mesh design for an integrated circuit device Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling... | 12/06/2011 |
| 8053848 | Semiconductor device and method of forming the same A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the device isolation layer and the transistors, and a guard region disposed ... | 11/08/2011 |
| 8039905 | Semiconductor device A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure o... | 10/18/2011 |
| 8039906 | High-voltage metal oxide semiconductor device and fabrication method thereof A high-voltage metal oxide semiconductor device comprising a main body of a first conductivity type, a conductive structure, a first well of a second conductivity type, a source region of the first conductivity type, and a second well of the second conductivity type... | 10/18/2011 |
| 8008734 | Power semiconductor device A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with large side etching or etching variation, which exhibits superior lon... | 08/30/2011 |
| 8004051 | Lateral trench MOSFET having a field plate One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes source and drain regions having a body region therebetween. A gate electrode region is disposed in a trench tha... | 08/23/2011 |
| 7999333 | Semiconductor device In a conventional semiconductor device, there has been a problem that, in a region where a wiring layer to which a high electric potential is applied traverses a top surface of an isolation region, the withstand voltage is deteriorated. In a semiconductor device of ... | 08/16/2011 |
| 7994589 | Semiconductor device and method for fabricating the same A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are i... | 08/09/2011 |
| 7948039 | Semiconductor device and method for fabricating the same A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are i... | 05/24/2011 |
| 7928518 | P-channel power MIS field effect transistor and switching circuit In a P-channel power MIS field effect transistor formed on a silicon surface having substantially a (110) plane, a gate insulation film is used which provides a gate-to-source breakdown voltage of 10 V or more, and planarizes the silicon surface, or contains Kr, Ar,... | 04/19/2011 |
| 7906821 | Semiconductor device A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed abov... | 03/15/2011 |
| 7880240 | Semiconductor device A semiconductor device has a high voltage circuit section disposed on a semiconductor substrate having a first conductivity. The high voltage circuit section has a well region with a second conductivity, a first heavily doped impurity region with the first conductiv... | 02/01/2011 |
| 7851873 | Semiconductor device and method of manufacturing the same The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide fi... | 12/14/2010 |
| 7843019 | Seal ring for mixed circuitry semiconductor devices In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Approp... | 11/30/2010 |
| 7843020 | High withstand voltage transistor and manufacturing method thereof, and semiconductor device adopting high withstand voltage transistor A high withstand voltage transistor is capable of preventing its gate oxidized film from being damaged by a surge voltage/current, and includes: a gate electrode provided in a trench formed on a semiconductor substrate; a source and a drain which are respectively fo... | 11/30/2010 |
| 7821082 | Method for increasing breaking down voltage of lateral diffused metal oxide semiconductor transistor A lateral diffused metal oxide semiconductor transistor is disclosed. A p-type bulk is disposed on a substrate. An n-type well region is disposed in the p-type bulk. A plurality of field oxide layers are disposed on the p-type bulk and the n-type well region. A gate... | 10/26/2010 |
| 7816744 | Gate electrodes of HVMOS devices having non-uniform doping concentrations A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying... | 10/19/2010 |
| 7804143 | Radiation hardened device A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed su... | 09/28/2010 |
| 7800187 | Trech-type vertical semiconductor device having gate electrode buried in rounded hump opening In a semiconductor device including a gate electrode buried in a trench of the device, the trench is constructed by a first opening with a uniform width the same as that of an upper portion of the first opening and a second opening beneath the first opening with a w... | 09/21/2010 |
| 7791148 | Semiconductor device A semiconductor device includes a transistor region, a first guard ring, a second guard ring, and a silicide region. A first-conductive-type transistor is formed in the transistor region. The first guard ring is a second-conductive-type first impurity diffusion laye... | 09/07/2010 |
| 7732877 | Gated diode with non-planar source region A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed ... | 06/08/2010 |
| 7719064 | High voltage CMOS devices A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that... | 05/18/2010 |
| 7709908 | High-voltage MOS transistor device A high-voltage transistor device has a substrate, an isolation structure, a source, a gate, a drain, a plurality of doped regions, a plurality of ion wells, and a first dielectric layer disposed on the substrate. The high-voltage transistor device further has a firs... | 05/04/2010 |
| 7675127 | MOSFET having increased snap-back conduction uniformity According to an exemplary embodiment, a semiconductor structure includes an NFET situated over a substrate. The semiconductor structure further includes a P+ substrate tie ring surrounded the NFET. The P+ substrate tie ring includes a salicide layer situated on a P+... | 03/09/2010 |
| 7667279 | Semiconductor device Disclosed is a semiconductor device which has a circuit-forming region. The semiconductor device has a semiconductor substrate, a plurality of insulating interlayer films, a guard ring, and a first MIM capacitor. The insulating interlayer films, which are stacked on... | 02/23/2010 |
| 7667280 | Semiconductor device Provided is a semiconductor device having a trench isolation structure and a high power supply voltage circuit section including at least a well region and a MOS transistor formed therein. The high power supply voltage circuit section includes a carrier capture regi... | 02/23/2010 |
| 7655992 | Semiconductor device The invention is directed to providing a resistor with high reliability. The invention is also directed to miniaturizing a semiconductor device having a MOS transistor and a resistor element on the same semiconductor substrate. An N-type well region is formed in a f... | 02/02/2010 |
| 7642608 | Dual isolation for image sensors Methods, methods of making, devices, and systems for image sensors that include isolation regions are disclosed. A semiconductor imager includes a pixel array and peripheral circuitry arranged on at least one side of the pixel array. Array devices are formed as part... | 01/05/2010 |
| 7629656 | Semiconductor device guard ring A semiconductor device 1 includes a semiconductor substrate 10, insulating interlayer group 20 (first insulating interlayer group), insulating interlayer group 30 (second insulating interlayer group), and seal ring 40 (guard ring).... | 12/08/2009 |
| 7595537 | MOS type semiconductor device having electrostatic discharge protection arrangement In a semiconductor device, a well region is formed in a semiconductor substrate, a transistor-formation region is defined in the well region. An electrostatic discharge protection device is produced in the transistor-formation region, and features a multi-finger str... | 09/29/2009 |
| 7564107 | Power semiconductor device including a terminal structure A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the tre... | 07/21/2009 |
| 7560787 | Trench field plate termination for power devices In accordance with an embodiment of the invention, a semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. A ... | 07/14/2009 |
| 7492018 | Isolating substrate noise by forming semi-insulating regions An integrated circuit structure for isolating substrate noise and a method of forming the same are provided. In the preferred embodiment of the present invention, a semi-insulating region is formed using proton bombardment in a substrate between a first circuit regi... | 02/17/2009 |
| 7489011 | Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region m... | 02/10/2009 |
| 7476947 | Semiconductor device and method of manufacturing the same A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conducti... | 01/13/2009 |
