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| Number | Title | Issue Date |
| 8415752 | Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone An asymmetric insulated-gate field effect transistor (100U or 102U) provided along an upper surface of a semiconductor body contains first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a c... | 04/09/2013 |
| 8390080 | Transistor with dopant-bearing metal in source and drain A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are recessed. The recesses are filled with a dopant-bearing metal, and a low-temperature anneal process is used... | 03/05/2013 |
| 8384167 | Semiconductor device with field effect transistor and manufacturing method thereof A semiconductor device includes: a semiconductor substrate in which a SiGe layer having a first width in a channel direction is embedded in a channel forming region; gate insulating film formed on the channel forming region; a gate electrode formed on the gate insul... | 02/26/2013 |
| 8350342 | Semiconductor device A semiconductor device includes a gate electrode provided on a semiconductor region with a gate insulating film being interposed therebetween, extension diffusion layers provided in regions on both sides of the gate electrode of the semiconductor region, a first-con... | 01/08/2013 |
| 8299546 | Semiconductor devices with vertical extensions for lateral scaling A method of forming a semiconductor device is provided, in which extension regions are formed atop the substrate in a vertical orientation. In one embodiment, the method includes providing a semiconductor substrate doped with a first conductivity dopant. Raised exte... | 10/30/2012 |
| 8288831 | Semiconductor device, method of manufacturing the same, and electronic device having the same A semiconductor device, which can improve the effect of a hydrogenation treatment in case of using a GOLD structure, and a method of manufacturing thereof is provided. A gate insulating film is formed on a semiconductor layer, and a source region, a drain region, an... | 10/16/2012 |
| 8253208 | Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile A gate dielectric layer (500, 566, or 700) of an insulated-gate field-effect transistor (110, 114, or 122) contains nitrogen having a vertical concentration profile specially tailored to prevent boron in the overlying gate electrode (5... | 08/28/2012 |
| 8222706 | Semiconductor device A semiconductor device includes, a gate insulating film, a gate electrode, a source/drain region, and a Si mixed crystal layer in the source/drain region. The Si mixed crystal layer includes a first Si mixed crystal layer that includes impurities with a first concen... | 07/17/2012 |
| 8217471 | System and method for metal-oxide-semiconductor field effect transistor System and method for metal-oxide-semiconductor field effect transistor. In a specific embodiment, the invention provides a field effect transistor (FET), which includes a substrate material, the substrate material being characterized by a first conductivity type, t... | 07/10/2012 |
| 8159036 | Semiconductor device and method of manufacturing the same A LDD layer of the second conduction type locates in the surface of a semiconductor layer beneath a sidewall insulator film. A source layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the LDD layer. A r... | 04/17/2012 |
| 8138559 | Recessed drift region for HVMOS breakdown improvement A high-voltage metal-oxide-semiconductor (HVMOS) device having increased breakdown voltage and methods for forming the same are provided. The HVMOS device includes a semiconductor substrate; a gate dielectric on a surface of the semiconductor substrate; a gate elect... | 03/20/2012 |
| 8106466 | MOS transistor and method for fabricating the same A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate... | 01/31/2012 |
| 8097924 | Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The... | 01/17/2012 |
| 8093665 | Semiconductor device and method for fabricating the same A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower t... | 01/10/2012 |
| 8053847 | Method for fabricating metal-oxide semiconductor transistors A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecu... | 11/08/2011 |
| 8022488 | High-performance FETs with embedded stressors A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a ... | 09/20/2011 |
| 7989901 | MOS devices with improved source/drain regions with SiGe A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a SiGe region in the semiconductor substrate and adjacent the gate stack, wherein th... | 08/02/2011 |
| 7973372 | Semiconductor structure in which source and drain extensions of field-effect transistor are defined with different dopants An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlie... | 07/05/2011 |
| 7956425 | Graded gate field Thin film transistors (TFT) and methods for making same. The TFTs generally comprise: (a) a semiconductor layer comprising source and drain terminals and a channel region therebetween; (b) a gate electrode comprising a gate and a gate dielectric layer between the ga... | 06/07/2011 |
| 7952152 | Semiconductor device and fabrication method thereof For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate... | 05/31/2011 |
| 7906820 | Source offset MOSFET optimized for current voltage characteristic invariance with respect to changing temperatures A semiconductor device is disclosed. The semiconductor device includes a source offset type MOS transistor in which a source and a drain are formed on a semiconductor substrate by having a predetermined distance between the source and the drain, and a gate electrode... | 03/15/2011 |
| 7888752 | Structure and method to form source and drain regions over doped depletion regions A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive ty... | 02/15/2011 |
| 7884427 | Applying epitaxial silicon in disposable spacer flow A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed si... | 02/08/2011 |
| 7868398 | Semiconductor device A semiconductor device, which can improve the effect of a hydrogenation treatment in case of using a GOLD structure, and a method of manufacturing thereof is provided. A gate insulating film is formed on a semiconductor layer, and a source region, a drain region, an... | 01/11/2011 |
| 7863693 | Forming conductive stud for semiconductive devices Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer r... | 01/04/2011 |
| 7863692 | Semiconductor device Embodiments relate to a semiconductor device in which a first oxide layer may be formed in a channel area under the gate electrode. An electric field loaded on the gate electrode may be reduced when electrons are implanted from the source to the drain, the accelerat... | 01/04/2011 |
| 7804142 | Semiconductor device and fabrication method thereof For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate... | 09/28/2010 |
| 7768078 | Power semiconductor device having improved performance and method In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a counter-doped drain region spaced apart from a channel region. ... | 08/03/2010 |
| 7759745 | Semiconductor memory device A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentr... | 07/20/2010 |
| 7737510 | Semiconductor device and method for fabricating the same A gate insulating film and a gate electrode are formed on an active region of a semiconductor substrate. A sidewall forming an L shape in cross section is formed on the sides of the gate electrode. Source/drain regions are formed in regions of the semiconductor subs... | 06/15/2010 |
| 7728393 | Semiconductor device A semiconductor device and method of manufacturing the semiconductor device are provided. The semiconductor device may include a semiconductor substrate, a gate insulation layer and a gate electrode, a first spacer, a second spacer, an epitaxial pattern, and/or sour... | 06/01/2010 |
| 7683440 | Semiconductor memory device A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentr... | 03/23/2010 |
| 7655991 | CMOS device with stressed sidewall spacers Sidewall spacers on the gate of a MOS device are formed from stressed material so as to provide strain in the channel region of the MOS device that enhances carrier mobility. In a particular embodiment, the MOS device is in a CMOS cell that includes a second MOS dev... | 02/02/2010 |
| 7649234 | Semiconductor devices An embodiment of a semiconductor device includes a gate electrode overlying a substrate and a lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo ... | 01/19/2010 |
| 7642607 | MOS devices with reduced recess on substrate surface A MOS device having reduced recesses under a gate spacer and a method for forming the same are provided. The MOS device includes a gate structure overlying the substrate, a sidewall spacer on a sidewall of the gate structure, a recessed region having a recess depth ... | 01/05/2010 |
| 7598575 | Semiconductor die with reduced RF attenuation The attenuation of an RF signal on a metal trace in a semiconductor die is substantially reduced by utilizing a number of RF blocking structures that lie on the surface of the substrate directly below the metal trace that carries the RF signal. The RF blocking struc... | 10/06/2009 |
| 7535065 | Thin film transistor device utilizing transistors of differing material characteristics A first insulating film is formed. Then, a gate electrode of a low voltage drive thin film transistor and a mask film for covering a region constituting a channel of a high voltage drive thin film transistor are formed with a molybdenum film on the first insulating ... | 05/19/2009 |
| 7525165 | Light emitting device and manufacturing method thereof The light emitting device according to the present invention is characterized in that a gate electrode comprising a plurality of conductive films is formed, and concentrations of impurity regions in an active layer are adjusted with making use of selectivity of the ... | 04/28/2009 |
| 7521768 | Electric device comprising an LDMOS transistor The LDMOS transistor (99) of the invention is provided with a stepped shield structure (50) and/or with a first (25) and a second (26) drain extension region having a higher dopant concentration than the second drain extension region, and... | 04/21/2009 |
| 7521767 | MOS transistor in a semiconductor device Methods of forming a MOS transistor and a MOS transistor fabricated thereby are provided. The MOS transistor includes a semiconductor substrate of a first conductivity type, and an insulated gate pattern having sidewalls disposed on a predetermined region of the sem... | 04/21/2009 |