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| Number | Title | Issue Date |
| 8384166 | Method for manufacturing semiconductor device and semiconductor device A semiconductor device manufacturing method includes the steps of: successively forming, on a semiconductor substrate, a gate insulating film and first and second dummy sections stacked in this order; forming a notch section by processing the gate insulating film an... | 02/26/2013 |
| 8384165 | Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selectiv... | 02/26/2013 |
| 8373239 | Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The re... | 02/12/2013 |
| 8294223 | Metal gate structure and method of manufacturing same A method of manufacturing a metal gate structure includes providing a substrate (110) having formed thereon a gate dielectric (120), a work function metal (130) adjacent to the gate dielectric, and a gate metal (140) adjacent to the work ... | 10/23/2012 |
| 8283734 | Multi-threshold voltage device and method of making same An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. An exemplary method includes providing a substrate; forming a first gate over the substrate for a first device having a first threshold voltage characteristic, the... | 10/09/2012 |
| 8237233 | Field effect transistor having a gate structure with a first section above a center portion of the channel region and having a first effective work function and second sections above edges of the channel region and having a second effective work function In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a f... | 08/07/2012 |
| 8169040 | Semiconductor device and method for manufacturing the same A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first so... | 05/01/2012 |
| 8159035 | Metal gates of PMOS devices having high work functions A semiconductor structure includes a refractory metal silicide layer; a silicon-rich refractory metal silicide layer on the refractory metal silicide layer; and a metal-rich refractory metal silicide layer on the silicon-rich refractory metal silicide layer. The ref... | 04/17/2012 |
| 8148787 | Semiconductor device and method for manufacturing the same There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS tra... | 04/03/2012 |
| 8106465 | Semiconductor device Provided is a semiconductor device in which occurrence of humps can be suppressed and variations in characteristics of the semiconductor device can be suppressed. The semiconductor device includes: an element isolation film (200) formed in a semiconductor lay... | 01/31/2012 |
| 8076735 | Semiconductor device with trench of various widths A semiconductor device and a method for fabricating the same are described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. ... | 12/13/2011 |
| 8030716 | Self-aligned CMOS structure with dual workfunction A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blan... | 10/04/2011 |
| 8013401 | Selectively depositing aluminum in a replacement metal gate process A method for carrying out a replacement metal gate process comprises providing a transistor in a reactor, wherein the transistor includes a gate stack, removing at least a portion of the gate stack to expose a surface of a barrier layer, causing a temperature of the... | 09/06/2011 |
| 8004050 | Semiconductor device comprising gate electrode having arsenic and phosphorous A semiconductor device is disclosed, which comprises a gate electrode having a laminated structure of a polycrystalline silicon film or a polycrystalline germanium film containing arsenic and a first nickel silicide layer formed in sequence on an element forming reg... | 08/23/2011 |
| 7999332 | Asymmetric semiconductor devices and method of fabricating A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the... | 08/16/2011 |
| 7989900 | Semiconductor structure including gate electrode having laterally variable work function A semiconductor structure, such as a CMOS structure, includes a gate electrode that has a laterally variable work function. The gate electrode that has the laterally variable work function may be formed using an angled ion implantation method or a sequential layerin... | 08/02/2011 |
| 7960802 | Methods to enhance effective work function of mid-gap metal by incorporating oxygen and hydrogen at a low thermal budget A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase ... | 06/14/2011 |
| 7936025 | Metalgate electrode for PMOS transistor Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to preven... | 05/03/2011 |
| 7872317 | Dual metal gate self-aligned integration A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon ... | 01/18/2011 |
| 7804141 | Semiconductor element structure and method for making the same A semiconductor element structure includes a first MOS having a first high-K material and a first metal for use in a first gate, a second MOS having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connec... | 09/28/2010 |
| 7800186 | Semiconductor device and method of fabricating metal gate of the same Provided is a semiconductor device and a method of fabricating a metal gate in the semiconductor device. The semiconductor device includes a metal gate formed on a gate insulating film, the metal gate is formed of a mixture of a metal nitride and a metal carbide, an... | 09/21/2010 |
| 7781848 | Semiconductor device with extension structure and method for fabricating the same A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source ex... | 08/24/2010 |
| 7768076 | Semiconductor device comprising an n-channel and p-channel MISFET A semiconductor device has an n-channel MISFET having first diffusion layers formed in a first region of a surface portion of a semiconductor substrate so as to sandwich a first channel region therebetween, a first gate insulating film formed on the first channel re... | 08/03/2010 |
| 7768077 | Semiconductor device and method for manufacturing the same A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first so... | 08/03/2010 |
| 7750418 | Introduction of metal impurity to change workfunction of conductive electrodes Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-conta... | 07/06/2010 |
| 7745888 | Method of making p-channel and n-channel MIS transistors using single film formation of TaC A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111... | 06/29/2010 |
| 7745887 | Dual work function metal gate structure and related method of manufacture A semiconductor device and related methods of manufacture are disclosed in which dual work function metal gate electrodes are formed from a single metal layer by doping the metal layer with carbon and/or fluorine. ... | 06/29/2010 |
| 7667277 | TiC as a thermally stable p-metal carbide on high k SiOgate stacks A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabri... | 02/23/2010 |
| 7667278 | Metal carbide gate structure and method of fabrication A semiconductor device such as a complementary metal oxide semiconductor (CMOS) including at least one FET that includes a gate electrode including a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes wh... | 02/23/2010 |
| 7612422 | Structure for dual work function metal gate electrodes by control of interface dipoles Exemplary embodiments provide structures for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or decreased by disposing various electronegative species and/or electropositive species at the metal/dielec... | 11/03/2009 |
| 7612421 | Electronic device with dopant diffusion barrier and tunable work function and methods of making same A method of fabricating a semiconductive film stack for use as a polysilicon germanium gate electrode to address problems associated with implant and diffusion of dopants. Achieving a sufficiently high active dopant concentration at a gate-dielectric interface while... | 11/03/2009 |
| 7579660 | Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating film. The gate electrode includes a conductive layer consisting... | 08/25/2009 |
| 7566937 | MOS transistor including multi-work function metal nitride gate electrode, COMS integrated circuit device including same, and related methods of manufacture Disclosed is a MOS transistor including a multi-work function metal nitride gate electrode. The MOS transistor comprises a semiconductor substrate and a central gate electrode formed on the semiconductor substrate. The central gate electrode is formed of a metal nit... | 07/28/2009 |
| 7541657 | Semiconductor device and method for manufacturing the same There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS tra... | 06/02/2009 |
| 7485936 | Semiconductor device and method of manufacturing the same It is possible to provide a semiconductor device including a CMOS device having a gate electrode, in which the variation in threshold voltage is little. There are a p-channel MIS transistor and a n-channel MIS transistor which are provided in a semiconductor substra... | 02/03/2009 |
| 7465999 | Fully-depleted (FD) (SOI) MOSFET access transistor A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed. ... | 12/16/2008 |
| 7439113 | Forming dual metal complementary metal oxide semiconductor integrated circuits Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer... | 10/21/2008 |
| 7439140 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 10/21/2008 |
| 7436034 | Metal oxynitride as a pFET material A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as w... | 10/14/2008 |
| 7435652 | Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite diff... | 10/14/2008 |
