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| Number | Title | Issue Date |
| 7944004 | Multiple thickness and/or composition high-K gate dielectrics and methods of making thereof Disclosed are methods of making an integrated circuit with multiple thickness and/or multiple composition high-K gate dielectric layers and integrated circuits containing multiple thickness and/or multiple composition high-K gate dielectrics. The methods involve for... | 05/17/2011 |
| 7875937 | Semiconductor device with a high-k gate dielectric and a metal gate electrode A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric lay... | 01/25/2011 |
| 7821081 | Method and apparatus for flatband voltage tuning of high-k field effect transistors In one embodiment, the invention is a method and apparatus for flatband voltage tuning of high-k field effect transistors. One embodiment of a field effect transistor includes a substrate, a high-k dielectric layer deposited on the substrate, a gate electrode deposi... | 10/26/2010 |
| 7759744 | Semiconductor device having high dielectric constant layers of different thicknesses A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET | 07/20/2010 |
| 7592678 | CMOS transistors with dual high-k gate dielectric and methods of manufacture thereof CMOS devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second... | 09/22/2009 |
| 7573110 | Method of fabricating semiconductor devices Method of fabricating TFTs (thin-film transistors) having a crystallized silicon film and a gate-insulating film. First, an amorphous silicon film is formed on an insulating substrate. A first dielectric film is formed from silicon oxide on the amorphous silicon fil... | 08/11/2009 |
| 7442999 | Semiconductor substrate, substrate for semiconductor crystal growth, semiconductor device, optical semiconductor device, and manufacturing method thereof A semiconductor substrate includes: a semiconductor crystal layer grown on one face of a substrate; and a stress relaxation layer, which is formed on the other face opposite to the one face and the side face of the substrate and applies stress to the substrate in th... | 10/28/2008 |
| 7442977 | Gated field effect devices This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the c... | 10/28/2008 |
| 7427791 | Method of forming a CMOS structure having gate insulation films of different thicknesses The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transist... | 09/23/2008 |
| 7423326 | Integrated circuits with composite gate dielectric CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface. ... | 09/09/2008 |
| 7420256 | Nonvolatile semiconductor memory device having a gate stack and method of manufacturing the same A nonvolatile semiconductor memory device includes a semiconductor substrate having a source region and a drain region, and a gate stack formed on the semiconductor substrate between and in contact with the source and drain regions. The gate stack includes, in seque... | 09/02/2008 |
| 7402873 | Semiconductor integrated circuit device having deposited layer for gate insulation A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transist... | 07/22/2008 |
| 7397094 | Semiconductor device and manufacturing method thereof To provide a semiconductor device that enables to suppress a defect density of a gate insulating film of an MISFET, gain a sufficient electric characteristic thereof, and make an Equivalent Oxide Thickness (EOT) of the gate insulating film 1.0 nm or less. The MISFET... | 07/08/2008 |
| 7372112 | Semiconductor device, process for producing the same and process for producing metal compound thin film A high dielectric gate insulating film having the structure that a high-nitrogen layer, a low-nitrogen layer, and a high-nitrogen layer are layered in this order from a silicon-substrate side. ... | 05/13/2008 |
| 7372113 | Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the ga... | 05/13/2008 |
| 7365389 | Memory cell having enhanced high-K dielectric A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory... | 04/29/2008 |
| 7361538 | Transistors and methods of manufacture thereof Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (... | 04/22/2008 |
| 7361561 | Method of making a metal gate semiconductor device A patterned polysilicon gate is over a metal layer that is over a gate dielectric layer, which in turn is over a semiconductor substrate. A thin layer of material is conformally deposited over the polysilicon gate and the exposed metal layer and then etched back to ... | 04/22/2008 |
| 7355249 | Silicon-on-insulator based radiation detection device and method Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the bu... | 04/08/2008 |
| 7348247 | Semiconductor devices and methods of manufacturing the same Semiconductor devices and methods of manufacturing the same are disclosed. A disclosed semiconductor device comprises a semiconductor substrate; a gate formed on the semiconductor substrate; a gate oxide layer interposed between the semiconductor substrate and the g... | 03/25/2008 |
| 7326988 | Semiconductor device and method for fabricating the same A metal film formed of a first metal having relatively high oxygen absorption properties on a silicon region, and then depositing a high dielectric constant film formed of an oxide of a second metal having relatively low oxygen absorption properties on the metal fil... | 02/05/2008 |
| 7323756 | Method of composite gate formation Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film... | 01/29/2008 |
| 7323755 | Method of composite gate formation Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film... | 01/29/2008 |
| 7312499 | Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and IC card A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function o... | 12/25/2007 |
| 7312491 | Charge trapping semiconductor memory element with improved trapping dielectric A semiconductor memory element, which can be controlled via field effect, includes a semiconductor substrate of a first conduction type, a first doping region of a second conduction type provided in the semiconductor substrate, a second doping region of the second c... | 12/25/2007 |
| 7304340 | Semiconductor storage elements, semiconductor device manufacturing methods therefor, portable electronic equipment and IC card A semiconductor storage element has a memory function body on opposite sides of a gate electrode formed on a semiconductor substrate. Each end of source/drain regions is located in the semiconductor substrate just under the memory function body and offset with respe... | 12/04/2007 |
| 7301219 | Electrically erasable programmable read only memory (EEPROM) cell and method for making the same An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to th... | 11/27/2007 |
| 7294547 | SONOS memory cell having a graded high-K dielectric A semiconductor memory device may include an intergate dielectric layer of high-K dielectric materials interposed between a charge storing layer and a control gate. The high-K materials may be deposited in such a manner that the materials are gradually graded with r... | 11/13/2007 |
| 7276770 | Fast Si diodes and arrays with high quantum efficiency built on dielectrically isolated wafers Fast silicon diodes and arrays with high quantum efficiency built on dielectrically isolated wafers. A waveguide is formed in the top surface of the silicon that utilizes total internal reflection from the Si—Si Oxide interface to form an internal mirror. This mir... | 10/02/2007 |
| 7273815 | Etch features with reduced line edge roughness A method for forming a feature in a layer with reduced line edge roughening is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A sidewall layer with a thickness less ... | 09/25/2007 |
| 7268393 | Semiconductor devices and methods of manufacturing the same Semiconductor devices and methods of manufacturing semiconductor devices which achieve higher integration and higher operating speed are provided. A disclosed example semiconductor device includes a semiconductor substrate of a first conductivity type; a gate insula... | 09/11/2007 |
| 7268401 | Semiconductor integrated circuit device having deposited layer for gate insulation A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transist... | 09/11/2007 |
| 7259433 | Non-volatile semiconductor memory device and method for producing same The memory device has a plurality of dielectric films including charge storage layers CS having a charge holding capability therein and stacked on an active region of a semiconductor SUB and electrodes G on the plurality of dielectric films. Each charge storage laye... | 08/21/2007 |
| 7247920 | Method of composite gate formation Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film... | 07/24/2007 |
| 7245010 | System and device including a barrier layer Systems and devices are disclosed utilizing a silicon-containing barrier layer. A semiconductor device is disclosed and includes a substrate, a gate oxide, a silicon-containing barrier layer and a gate electrode. The gate oxide is formed over the substrate. The sili... | 07/17/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
| 7238996 | Semiconductor device A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 1... | 07/03/2007 |
| 7224007 | Multi-channel transistor with tunable hot carrier effect A multiple channel transistor provides a transistor with an improved drive current and speed by using tunable hot carrier effects. A thin gate oxide has a carrier confinement layer formed on top thereof. Holes produced by hot carrier effects are retained by the carr... | 05/29/2007 |
| 7217977 | Covert transformation of transistor properties as a circuit protection method A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are ap... | 05/15/2007 |
| 7214986 | Semiconductor device, manufacturing method thereof, and display device A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel ... | 05/08/2007 |
