Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 8093664 | Non-volatile semiconductor memory device and depletion-type MOS transistor A peripheral circuit includes at least a first transistor. The first transistor comprises a gate electrode formed on a surface of a semiconductor layer via a gate insulating film. A channel region of a first conductivity type having a first impurity concentration is... | 01/10/2012 |
| 7442971 | Self-biasing transistor structure and an SRAM cell having less than six transistors By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect tran... | 10/28/2008 |
| 7432565 | III-V compound semiconductor heterostructure MOSFET device A III-V based, implant free MOS heterostructure field-effect transistor device comprises a gate insulator layer overlying a compound semiconductor substrate; ohmic contacts coupled to the compound semiconductor substrate proximate opposite sides of an active device ... | 10/07/2008 |
| 7417277 | Semiconductor integrated circuit and method of manufacturing the same Conventional capacitors constituted of a FET incur degradation in frequency response. A semiconductor integrated circuit includes a semiconductor substrate, an N-type FET, a P-type FET, and capacitors. The N-type FET includes N-type impurity diffusion layers, a P-ty... | 08/26/2008 |
| 7388260 | Structure for spanning gap in body-bias voltage routing structure Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire. ... | 06/17/2008 |
| 7385263 | Low resistance integrated MOS structure The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are pl... | 06/10/2008 |
| 7361947 | Photoelectric conversion element and display device including the same A photoelectric conversion element includes a semiconductor layer including a pair of p+ regions in which p-type impurities are doped, and a p− region which is disposed between the p+ regions and has a lower p-type impurity concent... | 04/22/2008 |
| 7348227 | Semiconductor device and manufacturing method thereof A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a ... | 03/25/2008 |
| 7326977 | Low noise field effect transistor An FET (field effect transistor) having source, drain and channel regions of a conductivity type in a semiconductor body of opposite conductivity type. The channel region is located at the lower extremity of the source and drain regions so as to be spaced from the s... | 02/05/2008 |
| 7319061 | Method for fabricating electronic device In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extensi... | 01/15/2008 |
| 7294935 | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misle... | 11/13/2007 |
| 7288817 | Reverse metal process for creating a metal silicide transistor gate structure The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate co... | 10/30/2007 |
| 7286389 | Low-power, p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells Low-power, all-p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells are disclosed. A PMOSFET SRAM cell is disclosed. The SRAM cell can include a latch having first and second PMOSFETs for storing data. Further, a gate of ... | 10/23/2007 |
| 7282768 | MOS field-effect transistor A high-reliable depletion-type MOS field-effect transistor as a process monitor is provided. A diode formed in polycrystalline silicon and a diode formed in a semiconductor substrate form a bi-directional diode. The bi-directional diode connects a gate electrode wit... | 10/16/2007 |
| 7279758 | N-channel MOSFETs comprising dual stressors, and methods for forming the same The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single... | 10/09/2007 |
| 7274056 | Semiconductor constructions The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. Th... | 09/25/2007 |
| 7274076 | Threshold voltage adjustment for long channel transistors A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel regi... | 09/25/2007 |
| 7271457 | Abrupt channel doping profile for fermi threshold field effect transistors A Fermi threshold voltage FET has Germanium implanted to form a shallow abrupt transition between the semiconductor substrate dopant type, or well dopant type, and a counter doping layer of opposite type closely adjacent the surface of the semiconductor substrate. G... | 09/18/2007 |
| 7247543 | Decoupling capacitor A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric m... | 07/24/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
| 7227227 | Reduced leakage semiconductor device The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. Th... | 06/05/2007 |
| 7217977 | Covert transformation of transistor properties as a circuit protection method A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are ap... | 05/15/2007 |
| 7186609 | Method of fabricating trench junction barrier rectifier A Schottky rectifier includes a rectifying interface between a semiconductor body and a metal layer. Trenches are formed in the surface of the semiconductor body and regions of a conductivity type opposite to the conductivity type of the body are formed along the si... | 03/06/2007 |
| 7187238 | Circuit for adjusting the operating point of multiple gate field effect transistors An amplifier circuit includes a first multiple gate field-effect transistor having a source terminal, a drain terminal, at least one signal gate terminal for receiving an input signal and at least one control gate terminal for receiving a control signal, and a secon... | 03/06/2007 |
| 7176530 | Configuration and fabrication of semiconductor structure having n-channel channel-junction field-effect transistor A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor (“IGFET”) (104) and an n-channel surface-channel IGFET (100 or 160) to reduce low-frequency 1/f noise. The channel-junction ... | 02/13/2007 |
| 7166515 | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering A camouflaged interconnection for interconnecting two spaced-apart regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first region forming a conducting channel between th... | 01/23/2007 |
| 7129544 | Vertical compound semiconductor field effect transistor structure In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel reg... | 10/31/2006 |
| 7098512 | Layout patterns for deep well region to facilitate routing body-bias voltage Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface ... | 08/29/2006 |
| 7081646 | Semiconductor device and method of fabricating same There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/d... | 07/25/2006 |
| 7078776 | Low threshold voltage semiconductor device A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed be... | 07/18/2006 |
| 7071518 | Schottky device A regular Schottky diode or a device that has a Schottky diode characteristic and an MOS transistor are coupled in series to provide a significant improvement in leakage current and breakdown voltage with only a small degradation in forward current. In the reverse b... | 07/04/2006 |
| 7049656 | Field-effect-controllable semiconductor configuration with a laterally extending channel zone A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first conductivity type, a channel zone of the first conductivity type, and at least one control electrode surround... | 05/23/2006 |
| 7049667 | Conductive channel pseudo block process and circuit to inhibit reverse engineering A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among... | 05/23/2006 |
| 7023060 | Methods for programming read-only memory cells and associated memories A method for programming a read-only memory cell including a transistor whose source and drain, which have a second type of doping, are formed in a semiconductor substrate with a first type of doping, includes a step of carrying out a contradoping in a region of the... | 04/04/2006 |
| 7019379 | Semiconductor device comprising voltage regulator element A semiconductor device includes a heavily doped layer 25 of p-type formed in the surface of an n-type well 21, an intermediately doped layer 26 of p-type formed to adjoin and surround the heavily p-doped layer 25, and an isolation region ... | 03/28/2006 |
| 7015546 | Deterministically doped field-effect devices and methods of making same Deterministically doped field-effect devices and methods of making same. One or more dopant atoms, also referred to as impurities or impurity atoms, are arranged in the channel region of a device in engineered arrays. Component atoms of an engineered array are subst... | 03/21/2006 |
| 7008873 | Integrated circuit with reverse engineering protection Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness... | 03/07/2006 |
| 6979606 | Use of silicon block process step to camouflage a false transistor A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is n... | 12/27/2005 |
| 6977408 | High-performance non-volatile memory device and fabrication process An EEPROM device exhibiting high saturation current and low signal propagation delay and a process for fabricating the device that includes the formation of refractory metal silicide regions in the source and the drain regions and the gate electrode of an MOS transi... | 12/20/2005 |
| 6972465 | CMOS process compatible, tunable negative differential resistance (NDR) device and method of operating same A CMOS based n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits a useful negative differential resistance effect is disclosed. The resulting device can be incorporated into a number of useful applications, including as part of a m... | 12/06/2005 |
