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| Number | Title | Issue Date |
| 7671424 | Power MOSFET, semiconductor device including the power MOSFET, and method for making the power MOSFET A metal oxide semiconductor field effect transistor includes a semiconductor substrate; a well region containing an impurity of a first conductivity type disposed on the semiconductor substrate, the well region including a source region and a drain region formed by ... | 03/02/2010 |
| 7633129 | Memory devices with active and passive layers having multiple self-assembled sublayers The present memory device includes first and second electrodes, an active layer and a passive layer, the active and passive layers being between the first and second electrodes, with either or both of the active layer and passive layer being made up a plurality of s... | 12/15/2009 |
| 7400018 | End of range (EOR) secondary defect engineering using chemical vapor deposition (CVD) substitutional carbon doping A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer... | 07/15/2008 |
| 7355226 | Power semiconductor and method of fabrication This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and method for their fabrication. A power semiconductor, the semiconductor comprising a po... | 04/08/2008 |
| 7271468 | High-voltage compatible, full-depleted CCD A charge coupled device for detecting electromagnetic and particle radiation is described. The device includes a high-resistivity semiconductor substrate, buried channel regions, gate electrode circuitry, and amplifier circuitry. For good spatial resolution and high... | 09/18/2007 |
| 7256925 | Flexible electrochromic device and method of manufacturing the same A flexible electrochromic device including a flexible transparent electrode including a predetermined pattern, an insulating layer formed on a portion of the transparent electrode other than the predetermined pattern, a semiconductor layer formed on the predetermine... | 08/14/2007 |
| 7250330 | Method of making an electronic package A method of making an electronic package is described, wherein a substrate is provided with a pattern of conductive pads and a portion of solder positioned on selected ones of the pattern of copper pads. The solder is then reflowed to form partial hemispherically sh... | 07/31/2007 |
| 7227235 | Electrowetting battery having a nanostructured electrode surface A method and apparatus are disclosed wherein a battery comprises an electrode having at least one nanostructured surface. The nanostructured surface is disposed in a way such that an electrolyte fluid of the battery is prevented from contacting the electrode, thus p... | 06/05/2007 |
| 7187039 | Semiconductor integrated circuit device Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections ... | 03/06/2007 |
| 7157374 | Method for removing a cap from the gate of an embedded silicon germanium semiconductor device A method of removing the cap from a gate of an embedded SiGe semiconductor device includes the formation of the embedded SiGe semiconductor device with the cap consisting of a cap material on top of the gate, first sidewall spacers on side surfaces of the gate, and ... | 01/02/2007 |
| 7049669 | LDMOS transistor A semiconductor device comprises an active region of a first conductivity type including a transistor structure, and a ring shaped region of the first conductivity type extending from a surface of the active region into the active region and substantially surroundin... | 05/23/2006 |
| 7022552 | Semiconductor device and method for fabricating semiconductor device A semiconductor device includes a semiconductor chip having an electrode pad electrically connected to an integrated circuit and a conducting part electrically connected to the electrode pad; an insulating material formed on a side of the semiconductor chip; and a c... | 04/04/2006 |
| 7019379 | Semiconductor device comprising voltage regulator element A semiconductor device includes a heavily doped layer 25 of p-type formed in the surface of an n-type well 21, an intermediately doped layer 26 of p-type formed to adjoin and surround the heavily p-doped layer 25, and an isolation region ... | 03/28/2006 |
| 7002210 | Semiconductor device including a high-breakdown voltage MOS transistor On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain fi... | 02/21/2006 |
| 6958537 | Multiple chip semiconductor package A semiconductor device package is disclosed. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace l... | 10/25/2005 |
| 6953961 | DRAM structure and fabricating method thereof A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure.... | 10/11/2005 |
| 6906355 | Semiconductor device A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the f... | 06/14/2005 |
| 6894354 | Trench isolated transistors, trench isolation structures, memory cells, and DRAMs An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isola... | 05/17/2005 |
| 6841837 | Semiconductor device A semiconductor device has: a gate insulator film of a transistor formed in a predetermined region on a region of a first conductivity type; a gate electrode of the transistor formed on the gate insulator film; a diffusion layer of a second conductivity type formed ... | 01/11/2005 |
| 6806541 | Field effect transistor with improved isolation structures An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from th... | 10/19/2004 |
| 6773995 | Double diffused MOS transistor and method for manufacturing same A method of manufacturing a semiconductor device, such as a double-diffused metal oxide semiconductor (DMOS) transistor, where a first layer may be formed on a semiconductor substrate, with isolation trenches formed in the first layer and semiconductor substrate, an... | 08/10/2004 |
| 6690074 | Radiation resistant semiconductor device structure A semiconductor device structure is described for reducing radiation induced current flow caused by incident ionizing radiation. The structure comprises a semiconductor substrate; two or more regions of a first conductivity type in the substrate; and a gu... | 02/10/2004 |
| 6518628 | Integrated CMOS circuit configuration, and production of same An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other ... | 02/11/2003 |
| 6365945 | Submicron semiconductor device having a self-aligned channel stop region and a method for fabricating the semiconductor device using a trim and etch A submicron semiconductor device having a self-aligned channel stop implant region, and a method for fabricating the semiconductor device using a trim and etch is disclosed. The semiconductor device includes a plurality of active regions separated by insu... | 04/02/2002 |
| 6323520 | Method for forming channel-region doping profile for semiconductor device A method for forming a semiconductor device with a doped channel-region, and the device formed therefrom. In one embodiment, the method invention is comprised of two principal steps. The first step is to provide a semiconductor substrate to which the foll... | 11/27/2001 |
| 6285073 | Contact structure and method of formation The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isola... | 09/04/2001 |
| 6194766 | Integrated circuit having low voltage and high voltage devices on a common semiconductor substrate High voltage and low voltage devices are provided on a common semiconductor substrate. An integrated semiconductor circuit includes a semiconductor substrate of a first conductivity type. Well regions of a first conductivity type and well regions of a sec... | 02/27/2001 |
| 6150213 | Method of forming a cob dram by using self-aligned node and bit line contact plug The present invention includes forming polysilicon plugs between the gate structures and word lines in a BPSG layer formed on the gate structures and the word lines. A polysilicon layer, a tungsten silicide layer and a silicon oxide layer are sequentially... | 11/21/2000 |
| 6087691 | Semiconductor device having lower minority carrier noise On a p++ substrate (1) provided is a p- epitaxial layer (2) having an impurity concentration lower than that of the p++ substrate (1). A p well (3) is formed in a portion of the p- epitaxial layer 2 and furthe... | 07/11/2000 |
| 6064110 | Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like... | 05/16/2000 |
| 6046475 | Structure and method for manufacturing devices having inverse T-shaped well regions A structure for manufacturing devices having inverse T-shaped well regions, which are formed on a substrate, comprises a first doped region and second doped region which have higher impurity concentrations and two third doped regions which have a lower im... | 04/04/2000 |
| 5994731 | Semiconductor device and fabrication method thereof A semiconductor device comprising a semiconductor substrate of a first conductivity type, an element separating field oxide film formed on the semiconductor substrate and a MOS transistor formed in an element area defined by the field oxide film. The MOS ... | 11/30/1999 |
| 5949116 | MOS device having a source/drain region conforming to a conductive material filled French structure in a substrate A MOS device and method of fabricating the same, wherein the source/drain region has polysilicon trench structure which are formed by self-alignment using silicon oxide layers as masks. The source/drain regions extend to the field oxide layer and/or above... | 09/07/1999 |
| 5883405 | MOS transistor read-only memory device A MOS semiconductor ROM device is provided which is capable of preventing an ion implantation region of one memory cell from overlapping into a region of an adjacent memory cell and causing a threshold voltage VT of the adjacent memory cell fro... | 03/16/1999 |
| 5880502 | Low and high voltage CMOS devices and process for fabricating same CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a sin... | 03/09/1999 |
| 5847426 | Contactless flash EPROM using poly silicon isolation A contactless flash EPROM cell array with poly 1 isolation blocks and process for its manufacture. The cell array includes poly 1 isolation blocks that are spaced-apart from a pair of drain lines of adjacent cells along a poly 2 word line in a manner that... | 12/08/1998 |
| 5841163 | Integrated circuit memory devices having wide and narrow channel stop layers An integrated circuit memory device includes a semiconductor substrate having a memory cell area and a select transistor area. A first field insulation layer is included in the memory cell area, and a first channel stop impurity layer is included beneath ... | 11/24/1998 |
| 5828108 | Semiconductor integrated circuit suppressing noises due to short-circuit/substrate currents A semiconductor integrated circuit has a semiconductor substrate on which macrocells are formed. At least one of the macrocells is surrounded by a first diffused region, which may be surrounded by a second diffused region. The first and second diffused re... | 10/27/1998 |
| 5789789 | Semiconductor device and manufacturing method for improved voltage resistance between an N-well and N-type diffusion layer A manufacturing method for a semiconductor device is disclosed for effecting improvement of voltage resistance between an N-well and N-type diffusion layer without adversely affecting circuit and transistor characteristics. At the time of forming an N-wel... | 08/04/1998 |
| 5751042 | Internal ESD protection circuit for semiconductor devices An internal electrostatic discharge (ESD) protection circuit for semiconductor devices defines a structure for protecting adjacent n-channel devices. The first n-channel device includes a pair of n+ regions defining source and drain regions wherein the dr... | 05/12/1998 |
