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| Number | Title | Issue Date |
| 5977597 | Layout structure of semiconductor memory with cells positioned in translated relation in first and second directions A layout structure of an SRAM for reductions in the number of interconnect layers and in the number of connection holes with conventional advantages maintained is disclosed. Contact holes and fields which have been shared between cells vertically adjacent... | 11/02/1999 |
| 5965923 | Lateral bipolar transistor and apparatus using same A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral ... | 10/12/1999 |
| 5959334 | Semiconductor memory device A bipolar transistor is formed by forming a base region continuing from a source/drain region of an MOS transistor, as a link base region, and forming an emitter region at a bit line contact hole by impurity implantation. Alternatively, the bipolar transi... | 09/28/1999 |
| 5955770 | Method of forming raised source/drain regions in an integrated circuit A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of field oxide regions are formed overlying a substrate electrically isolating a plurality of t... | 09/21/1999 |
| 5953603 | Method for manufacturing BiCMOS Disclosed is a method for manufacturing a BiCMOS in which a complementary MOS transistor and a bipolar transistor are formed on the same substrate, comprising the steps of: providing a semiconductor substrate with impurities of a first conductivity type; ... | 09/14/1999 |
| 5949128 | Bipolar transistor with MOS-controlled protection for reverse-biased emitter-base junction A bipolar transistor with MOS-controlled protection for a reverse-biased emitter-base junction is disclosed. A bipolar transistor and a MOS transistor are configured with the drain and the gate electrically coupled to the emitter, and the source and body ... | 09/07/1999 |
| 5936288 | Semiconductor integrated circuit device and low breakdown voltage zener diode Anode and cathode regions at a principal surface of a semiconductor substrate have the same characteristics as source and drain regions of a P type MOS transistor. A cathode region is superposed partially on the anode region at the principal surface of th... | 08/10/1999 |
| 5917222 | Intergrated circuit combining high frequency bipolar and high power CMOS transistors A process flow which can be used to fabricate a high frequency bipolar transistor 147, a power transistor 146, and non-power MOS devices on a single substrate while maintaining superior performance. The process flow forms an initial high-voltage tank 170 ... | 06/29/1999 |
| 5910674 | Semiconductor integrated circuit device and method of fabricating the same A semiconductor integrated circuit device wherein a semiconductor layer of a second conductivity type is formed at a region excluding a region where a semiconductor element of the second conductivity type is formed, or at a region having an adequate area ... | 06/08/1999 |
| 5910675 | Semiconductor device and method of making the same A semiconductor device includes a metal terminal provided on a semiconductor substrate and a protection element. The protection element includes an insulated gate field-effect transistor. The transistor has a first diffusion layer of a reverse conductive-... | 06/08/1999 |
| 5910676 | Method for forming a thick base oxide in a BiCMOS process A BiCMOS structure and a method for making the same is disclosed, where the dielectric layer between the emitter electrode and the base region is formed of a deposited dielectric. After definition of the bipolar and MOS moat regions, a layer of polysilico... | 06/08/1999 |
| 5899714 | Fabrication of semiconductor structure having two levels of buried regions Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated... | 05/04/1999 |
| 5892263 | CMOS device connected to at least three power supplies for preventing latch-up A complementary metal-oxide-semiconductor device having a semiconductor region of an n conductivity type connected to a high-potential power supply, in which a p-channel MOSFET is formed, and a semiconductor region of a p conductivity type connected to a ... | 04/06/1999 |
| 5886387 | BiCMOS semiconductor integrated circuit device having MOS transistor and bipolar transistor regions of different thickness Disclosed are a semiconductor integrated circuit device capable of including both a bipolar transistor and a MOS transistor while maintaining high performances of then both and a method of fabricating the device. On a p-type silicon substrate a plurality ... | 03/23/1999 |
| 5880002 | Method for making isolated vertical PNP transistor in a digital BiCMOS process A vertical PNP transistor (11) and method for making it includes forming an N- region (19) in a P substrate (12), and forming an N+ region (26) in the substrate (12) laterally surrounding and partially extending into the N- region (19). A P region (30) is... | 03/09/1999 |
| 5856218 | Bipolar transistor formed by a high energy ion implantation method In an NPN bipolar transistor having a special structure in which each impurity region is formed by ion implantation, a width of a base region is significantly reduced, and therefore, current amplification factor hfe is increased, resulting in improvement ... | 01/05/1999 |
| 5856697 | Integrated dual layer emitter mask and emitter trench for BiCMOS processes A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in ... | 01/05/1999 |
| 5856695 | BiCMOS devices A BiCMOS process which provides both low voltage (digital) and high voltage (analog) CMOS devices. The high voltage NMOS devices have a compensated drain formed by the NPN and PNP base implants. The PNP base plus the high voltage NMOS drain carrier concen... | 01/05/1999 |
| 5844268 | Nonvolatile semiconductor memory device A select MOS transistor and a data storage MOS transistor are formed in an element region. The transistor has floating-gate electrodes. The floating-gate electrodes are spaced apart above the element region and connected to each other above a field region... | 12/01/1998 |
| 5844280 | Device for protecting a semiconductor circuit A protection device for protecting a semiconductor circuit from positive and negative overvoltage such as static electrical discharges. A p-type substrate is provided having a pair of spaced apart n-type regions formed therein. Each of the spaced apart n-... | 12/01/1998 |
| 5840603 | Method for fabrication BiCMOS integrated circuit A first photoresist layer has opening portions in a region where an n-channel MOS transistor should be formed and in a region where a collector leading region should be formed. Then, phosphorous is implanted with taking the first photoresist layer as a ma... | 11/24/1998 |
| 5838048 | Semiconductor Bi-MIS device A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are pattern... | 11/17/1998 |
| 5828109 | Semi-conductor integrated circuit device In a semi-conductor integrated circuit device, electric charges which relate to latch-up phenomenon generation are absorbed effectively, and thereby generation of the latch-up phenomenon is prevented. Low-concentration impurity diffusion layers of I/O tra... | 10/27/1998 |
| 5828110 | Latchup-proof I/O circuit implementation An arrangement that prevents triggering of latchup in internal circuits by input/output buffers on an integrated circuit chip provides a space surrounding each active device connected to a bond pad. A ring well surrounds the space and separates the active... | 10/27/1998 |
| 5828263 | Field effect-controllable power semiconductor component with temperature sensor A temperature sensor contains a bipolar transistor adjacent a cell array of a power MOSFET or IGBT. In order to detect temperature independently of a voltage drop across the power semiconductor component, a zone of the same conduction type is disposed bet... | 10/27/1998 |
| 5811860 | Bi-CMOS merged devices A merged BiCMOS device 10 having a bipolar transistor 60 and a PMOS transistor 64 formed in the same well region 18. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. Emitter elec... | 09/22/1998 |
| 5801418 | High voltage power integrated circuit with level shift operation and without metal crossover Level shift devices are formed in the high voltage termination region of an integrated circuit. The level shift devices provide a connection between the higher voltage, floating circuit and a ground referenced lower voltage circuit. The structure of the l... | 09/01/1998 |
| 5798552 | Transistor suitable for high voltage circuit A method and an apparatus for forming a transistor suitable for a high voltage circuit. In one embodiment, the transistor is formed without adding any steps to an existing state-of-the-art CMOS process. A well is implanted into a portion of a substrate su... | 08/25/1998 |
| 5793085 | Bipolar transistor compatible with CMOS processes A bipolar transistor, comprising a collector region, a base region, and an emitter region, is a type which is compatible to CMOS processes leading to the formation, on a semiconductor substrate, of N-channel and P-channel MOS transistors having respective... | 08/11/1998 |
| 5789790 | Semiconductor device A semiconductor device has a transistor made of a semiconductor which has a source and drain regions, a channel region, a gate insulative film, and a gate electrode. The gate electrode is connected to a part of the channel region. The channel region has t... | 08/04/1998 |
| 5780329 | Process for fabricating a moderate-depth diffused emitter bipolar transistor in a BICMOS device without using an additional mask A bipolar transistor with a relatively deep emitter region is formed in a BICMOS device using the source/drain mask used to form the source and drain regions of MOSFETs of the device and the base region mask which would otherwise be required in any event ... | 07/14/1998 |
| 5777510 | High voltage tolerable pull-up driver and method for operating same A pull-up output driver circuit includes a field effect transistor (FET) fabricated in a well region having a first conductivity type. The well region, in turn, is surrounded by a semiconductor region having a second conductivity type. The FET has a sourc... | 07/07/1998 |
| 5767551 | Intergrated circuit combining high frequency bipolar and high power CMOS transistors A process flow which can be used to fabricate a high frequency bipolar transistor 147, a power transistor 146, and non-power MOS devices on a single substrate while maintaining superior performance. The process flow forms an initial high-voltage tank 170 ... | 06/16/1998 |
| 5763920 | Semiconductor integrated circuit having bipolar and MOS transistors formed on a single semiconductor substrate A "BiCMOS" semiconductor integrated circuit, a gate oxide film 110 and a polysilicon film are grown on a semiconductor substrate, and after phosphorus is doped, the polysilicon film is patterned to form gate electrodes 112a and 112b and an emitter electro... | 06/09/1998 |
| 5759883 | Method for making semiconductor device capable of independently forming MOS transistors and bipolar transistor In a method of manufacturing a semiconductor integrated circuit device composed of a bipolar transistor and metal-oxide-semiconductor (MOS) transistors, first and second gate electrode structures are formed to have polysilicon layers having no impurity im... | 06/02/1998 |
| 5760448 | Semiconductor device and a method for manufacturing the same A semiconductor device having an electrostatic discharge protection device and at least one accompanying device selected from the group comprising of a N or P channel MOS transistor, CMOS, bipolar transistor and BiCMOS, in which the electrostatic discharg... | 06/02/1998 |
| 5751054 | Zener diodes on the same wafer with BiCDMOS structures A semiconductor structure which includes zener diodes and various combinations of MOS transistors, bipolar transistors and DMOS transistors, all fabricated on the same integrated circuit chip... | 05/12/1998 |
| 5744844 | CMOS SRAM cell An outline of an SRAM cell is rectangular. The SRAM cell have nMOS transistors QN1 and QN3 in a nMOS region 13A being on one side of the longitudinal direction, nMOS transistors QN2 and QN4 in a nMOS region 13B being on the opposite side thereof, pMOS tra... | 04/28/1998 |
| 5744855 | Single-poly-type bipolar transistor In a bipolar transistor of a type in which metal electrodes are formed in direct contact with a p-type external base region and an n-type collector region, respectively, an external base region surrounding an outer periphery of an n-type emitter region is... | 04/28/1998 |
| 5731617 | Semiconductor device having bipolar transistor and field effect transistor A semiconductor device with a reduced insulating capacitance between an emitter electrode and a base layer, and a manufacturing method thereof are disclosed. In the semiconductor device, at least first and second insulating layers are interposed between t... | 03/24/1998 |
