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...that Kleenex tissue was originally designed to be a gas mask filter? It was developed at the beginning of World War I to replace cotton, which was then in short supply as a surgical dressing.
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| Number | Title | Issue Date |
| 8188547 | Semiconductor device with complementary transistors that include hafnium-containing gate insulators and metal gate electrodes A first adjusting metal, capable of varying the threshold voltage of a first-conductivity-type transistor of a complementary transistor, is added to the first-conductivity-type transistor and a second-conductivity-type transistor at the same time, and a diffusion su... | 05/29/2012 |
| 8183640 | Method of fabricating transistors and a transistor structure for improving short channel effect and drain induced barrier lowering A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial l... | 05/22/2012 |
| 8183642 | Gate effective-workfunction modification for CMOS CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control lay... | 05/22/2012 |
| 8183641 | Semiconductor device and method for manufacturing same A silicon oxynitride film is formed on entire surface of a semiconductor substrate, a lanthanum oxide film is formed on the silicon oxynitride film and the lanthanum oxide film is removed from a pMOS region. Then, a nitrided hafnium silicate film serving as a highly... | 05/22/2012 |
| 8178929 | Semiconductor device and method for fabricating the same A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS t... | 05/15/2012 |
| 8174079 | Semiconductor device having a silicide gate electrode A semiconductor device includes a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; a silicide gate electrode of an n-type MISFET formed on the gate insulation film; and a silicide gate electrode of a p-type MISFET formed on the ... | 05/08/2012 |
| 8174080 | Semiconductor device A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected f... | 05/08/2012 |
| 8169033 | Semiconductor devices and methods of manufacture thereof Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectr... | 05/01/2012 |
| 8169032 | Gate stacks and semiconductor constructions The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride ... | 05/01/2012 |
| 8169031 | Continuous metal semiconductor alloy via for interconnects A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located ato... | 05/01/2012 |
| 8159034 | Semiconductor device having insulated gate field effect transistors and method of manufacturing the same N-type semiconductor region and P-type semiconductor region are provided in a surface region of a semiconductor substrate. Insulating film and silicon containing film are laminated on the semiconductor substrate. P-type impurities are introduced into a first portion... | 04/17/2012 |
| 8154084 | Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantat... | 04/10/2012 |
| 8143675 | Semiconductor device and method of manufacturing semiconductor device The semiconductor device includes an n-channel transistor including n-type source/drain regions and a first gate electrode, a first sidewall insulating film formed on a side wall of the first gate electrode and having a Young's modulus smaller than a Young's modulus... | 03/27/2012 |
| 8138552 | Semiconductor device and method of manufacturing the same A semiconductor device according to an embodiment of the present invention includes a substrate, a gate insulation film formed on the substrate, a gate electrode formed on the gate insulation film, sidewall insulation films provided on side surfaces of the gate elec... | 03/20/2012 |
| 8129796 | Semiconductor device There is provided a high-integrated complementary metal-oxide semiconductor static random-access memory including an inverter. The inverter includes: a first pillar that is formed by integrating a first-conductivity-type semiconductor, a second-conductivity-type sem... | 03/06/2012 |
| 8129795 | Inducing strain in the channels of metal gate transistors In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transisto... | 03/06/2012 |
| 8129793 | Semiconductor integrated device and manufacturing method for the same A first exemplary aspect of an exemplary embodiment of the present invention is a semiconductor integrated device comprising a semiconductor substrate, a first impurity layer of a first conductivity type formed in the semiconductor substrate, a second impurity layer... | 03/06/2012 |
| 8129794 | Semiconductor device including MISFETs having different threshold voltages A semiconductor device includes a first MIS transistor, and a second MIS transistor having a threshold voltage higher than that of the first MIS transistor. The first MIS transistor includes a first gate insulating film made of a high-k insulating film formed on a f... | 03/06/2012 |
| 8129792 | Semiconductor device and method for manufacturing the same A semiconductor device includes n- and p-type semiconductor regions separately formed on a substrate, an interlayer insulator formed on the substrate and having first and second trenches formed to reach the n- and p-type regions. There are further included first and... | 03/06/2012 |
| 8125035 | CMOS fabrication process Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverse... | 02/28/2012 |
| 8120118 | Semiconductor device and manufacturing method of the same Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactu... | 02/21/2012 |
| 8120116 | Semiconductor device and photomask Shared contact holes SC1 and SC2 reach both gate electrode layers GE1 and GE2 and a drain region PIR. In a planar view, a sidewall E2 of gate electrode layers GE1 and GE2 is shifted toward a side of a sidewall E4 | 02/21/2012 |
| 8120117 | Semiconductor device with metal gate Gate electrode structures having a thin layer of ReO3 formed with high effective work function and high heat resistance are disclosed. The thin layer of ReO3 is formed by providing a semiconductor structure having an oxygen-containing metal all... | 02/21/2012 |
| 8115257 | Semiconductor apparatus A semiconductor apparatus includes an internal circuit, a CMOS composed of a P-channel MOS transistor with a source connected to a high-potential power supply line and a gate connected to the internal circuit, and an N-channel MOS transistor with a source connected ... | 02/14/2012 |
| 8106462 | Balancing NFET and PFET performance using straining layers An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-pro... | 01/31/2012 |
| 8097922 | Nanometer-scale transistor architecture providing enhanced carrier mobility The present invention provides a nanometer-scale transistor architecture providing enhanced carrier mobility. In particular, a portion of a channel of a transistor is substantially surrounded with an acoustically hard material to form a barrier shell about the chann... | 01/17/2012 |
| 8093659 | Three-dimensional stacked-fin-MOS device with multiple gate regions The invention provides a three-dimensional stacked fin metal oxide semiconductor (SF-MOS) device (10,30) comprising a protrusion or fin structure with a plurality of stacked semiconductor regions (3,5,12), in which a second semiconductor region (5,1... | 01/10/2012 |
| 8089129 | Isolated CMOS transistors Isolated CMOS transistors formed in a P-type semiconductor substrate include an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and th... | 01/03/2012 |
| 8084824 | Metal gate transistor and method for fabricating the same A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k diele... | 12/27/2011 |
| 8084827 | Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo poc... | 12/27/2011 |
| 8084825 | Trilayer resist scheme for gate etching applications A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme... | 12/27/2011 |
| 8084826 | Semiconductor device and manufacturing method thereof An element larger than silicon is ion-implanted to a contact liner in an N-channel region to break constituent atoms of the contact liner in the N-channel region. An element larger than silicon is ion-implanted to the contact liner in a P-channel region to break con... | 12/27/2011 |
| 8084828 | Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first ga... | 12/27/2011 |
| 8076732 | Semiconductor device A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the f... | 12/13/2011 |
| 8076731 | Semiconductor device including a halo layer and method of fabricating the same A semiconductor device 1 according to one embodiment of the invention includes: a semiconductor substrate 10; a convex region 12 provided on the semiconductor substrate 10; a gate insulating film 100 provided on the convex region | 12/13/2011 |
| 8067806 | Gate structures of CMOS device and method for manufacturing the same Gate structures of CMOS device and the method for manufacturing the same are provided. A substrate having an NMOS region, a PMOS region, and a work function modulation layer disposed on the NMOS region and the PMOS region is provided. A nitrogen doping process is pe... | 11/29/2011 |
| 8058690 | Integration of planar and tri-gate devices on the same substrate An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain; a second diffusion formed on the substrate, the second diffusion including a channel that separates a sou... | 11/15/2011 |
| 8058691 | Semiconductor device including cross-coupled transistors formed from linear-shaped gate level features A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated... | 11/15/2011 |
| 8053842 | Semiconductor storage device It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in a Loadless 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors, each of the MOS transistor constituting the memor... | 11/08/2011 |
| 8053841 | Semiconductor device having a fin transistor A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation laye... | 11/08/2011 |
