Bizarre Patents
A method of swing on a swing is disclosed, in which a user positioned on a standard swing suspended by two chains from a substantially horizontal tree branch induces side to side motion by pulling alternately on one chain and then the other.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8445967 | Semiconductor switching device employing a quantum dot structure A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a th... | 05/21/2013 |
| 8405154 | Low cost transistors using gate orientation and optimized implants An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the... | 03/26/2013 |
| 8405153 | Semiconductor device A semiconductor device includes an active region formed in a substrate; an isolation structure formed to surround the active region; and one or more dummy regions formed between the active region and the isolation structure to extend integrally from the active regio... | 03/26/2013 |
| 8399929 | Semiconductor integrated circuit device To provide a technique that can maintain uniformity of semiconductor elements and wirings microfabricated, while maintaining the mounting efficiency of circuit cells onto a chip. Respective gate electrodes of an n-channel type MISFET and another n-channel type MISFE... | 03/19/2013 |
| 8399930 | Method of manufacturing a semiconductor device having a contact plug There is provided a semiconductor device that includes: a transistor having a gate electrode, a source region, and a drain region; a first inter-layer insulation film covering the transistor; a first contact plug formed penetrating through the first inter-layer insu... | 03/19/2013 |
| 8395220 | Nanomesh SRAM cell Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a dr... | 03/12/2013 |
| 8395219 | Semiconductor device and fabrication method for the same The semiconductor device includes a first transistor and a second transistor formed in a semiconductor substrate. The first transistor includes: a first gate insulating film formed on the semiconductor substrate; and a first gate electrode formed on the first gate i... | 03/12/2013 |
| 8395218 | Gate-all-around type semiconductor device and method of manufacturing the same The gate-all-around (GAA) type semiconductor device may include source/drain layers, a nanowire channel, a gate electrode and an insulation layer pattern. The source/drain layers may be disposed at a distance in a first direction on a semiconductor substrate. The na... | 03/12/2013 |
| 8378425 | Semiconductor storage device It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in a CMOS 6T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using six MOS transistors, each of the MOS transistor constituting the memory cel... | 02/19/2013 |
| 8373235 | Semiconductor memory device and production method therefor In a static memory cell comprising six MOS transistors, the MOS transistors have a structure in which the drain, gate and source formed on the substrate are arranged in the vertical direction and the gate surrounds the columnar semiconductor layer, the substrate com... | 02/12/2013 |
| 8373234 | Semiconductor device and method for forming the same A semiconductor device includes a structure in which a difference in height between a cell region and a peripheral region are formed so that a buried gate structure of the cell region is substantially equal in height to the gate of the peripheral region, whereby a b... | 02/12/2013 |
| 8373233 | Highly N-type and P-type co-doping silicon for strain silicon application A semiconductor device includes a gate, a source region and a drain region that are co-doped to produce a strain in the channel region of a transistor. The co-doping can include having a source and drain region having silicon that includes boron and phosphorous or a... | 02/12/2013 |
| 8368146 | FinFET devices A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of t... | 02/05/2013 |
| 8362567 | Semiconductor device In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance ... | 01/29/2013 |
| 8362568 | Recessed contact for multi-gate FET optimizing series resistance A transistor, which can be referred to as a multi-gate transistor or as a FinFET, includes a gate structure having a length, a width and a height. The transistor further includes at least one electrically conductive channel or fin between a source region and a drain... | 01/29/2013 |
| 8362566 | Stress in trigate devices using complimentary gate fill materials Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate metho... | 01/29/2013 |
| 8357977 | Semiconductor device and method for manufacturing same A method for manufacturing a semiconductor device, which includes the steps of: forming a mask layer (20) on a gate insulating film (18), the mask layer (20) having openings over the portions of first and second semiconductor layers that are des... | 01/22/2013 |
| 8357978 | Methods of forming semiconductor devices with replacement gate structures Disclosed herein are various methods of forming replacement gate structures on semiconductor devices and devices incorporating such gate structures. In one example, the device includes a plurality of gate structures and at least one sidewall spacer positioned proxim... | 01/22/2013 |
| 8354725 | MIM transistor The invention concerns a conducting layer having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer. ... | 01/15/2013 |
| 8350330 | Dummy pattern design for reducing device performance drift A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and add... | 01/08/2013 |
| 8344459 | Semiconductor device The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET ... | 01/01/2013 |
| 8338893 | Method and resulting structure DRAM cell with selected inverse narrow width effect A shallow trench isolation structure for integrated circuits includes a semiconductor substrate having a trench and a buffered oxide layer overlying the semiconductor substrate. A pad nitride layer is overlying the buffered oxide layer. An implanted region is formed... | 12/25/2012 |
| 8338892 | Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by corner rounding at the top of the gate electrode In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residue... | 12/25/2012 |
| 8338891 | Arrangement of MOSFET's for controlling same An arrangement of a plurality of MOSFET's on a chip that includes a first terminal, a second terminal and a third terminal is provided, the arrangement having at least one first MOSFET used as a first control cell and at least one second MOSFET used as a second cont... | 12/25/2012 |
| 8334573 | Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer... | 12/18/2012 |
| 8330225 | NMOS transistor devices and methods for fabricating same NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, an NMOS transistor may include a transistor stack comprising a gate dielectric and a gate electrode formed ato... | 12/11/2012 |
| 8330226 | Phase-change random access memory devices with a phase-change nanowire having a single element A PRAM device includes a lower electrode, a phase-change nanowire and an upper electrode. The phase-change nanowire may be electrically connected to the lower electrode and includes a single element. The upper electrode may be electrically connected to the phase-cha... | 12/11/2012 |
| 8324690 | Semiconductor device with multi-functional dielectric layer A composite dielectric layer including a tensile stressed nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patte... | 12/04/2012 |
| 8304835 | Configuration and fabrication of semiconductor structure using empty and filled wells A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), t... | 11/06/2012 |
| 8299536 | Semiconductor device having transistors each having gate electrode of different metal ratio and production process thereof A semiconductor device with integrated MIS field-effect transistors includes a first transistor including a first gate electrode having a composition represented by MAx, and a second transistor including a second gate electrode having a composition represented by MA... | 10/30/2012 |
| 8299535 | Delta monolayer dopants epitaxy for embedded source/drain silicide Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain exte... | 10/30/2012 |
| 8294216 | Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode o... | 10/23/2012 |
| 8294217 | Semiconductor device and method of manufacturing semiconductor device The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insul... | 10/23/2012 |
| 8288824 | Semiconductor device including insulated gate bipolar transistor and diode A semiconductor device includes a vertical IGBT and a vertical free-wheeling diode in a semiconductor substrate. A plurality of base regions is disposed at a first-surface side portion of the semiconductor substrate, and a plurality of collector regions and a plural... | 10/16/2012 |
| 8278717 | Semiconductor memory device and method of manufacturing the same In one embodiment, a semiconductor memory device includes a semiconductor substrate, and isolation layers formed in a surface of the semiconductor substrate, and separating the semiconductor substrate into active areas, the isolation layers and the active areas bein... | 10/02/2012 |
| 8274116 | Control of threshold voltages in high-k metal gate stack and structures for CMOS devices A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielect... | 09/25/2012 |
| 8269285 | Semiconductor device According to one embodiment, it is possible to provide a semiconductor device provided with an MIS transistor which has an effective work function being, as much as possible, suitable for low threshold operation. A CMIS device provided with an electrode having an op... | 09/18/2012 |
| 8269283 | Methods and apparatus to reduce layout based strain variations in non-planar transistor structures The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the ... | 09/18/2012 |
| 8269284 | Method of manufacturing semiconductor device, and semiconductor device There are provided a method of manufacturing a semiconductor device which achieves a reduction in implantation masks, and such a semiconductor device. By implanting boron into NMOS regions using a resist mask and another resist mask as the implantation masks, p-type... | 09/18/2012 |
| 8258578 | Handshake structure for improving layout density A semiconductor device includes a gate on a semiconductor substrate. One side wall of the gate may include at least one protrusion and an opposite side wall of the gate may include at least one depression. A contact is formed through an insulating layer disposed ove... | 09/04/2012 |
