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| Number | Title | Issue Date |
| 8183637 | Semiconductor device There is provided a semiconductor device including: a field effect transistor that is provided with a gate region, a drain region and a source region and that is formed on a substrate; a circuit region that is formed on the substrate so as to be electrically isolate... | 05/22/2012 |
| 8129789 | Current control using thermally matched resistors A semiconductor chip includes a semiconductor body having an upper surface. At least one power semiconductor component is integrated in the semiconductor chip together with other circuitry. Two or more vertically spaced metallization layers are arranged on the surfa... | 03/06/2012 |
| 8080852 | Semiconductor device and method of manufacturing the same The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating fil... | 12/20/2011 |
| 8013394 | Integrated circuit having resistor between BEOL interconnect and FEOL structure and related method Integrated circuits (IC) and a method of fabricating an IC, where the structure of the IC incorporates a back-end-of-the-line (BEOL) thin film resistor below a first metal layer to achieve lower topography are disclosed. The resistor directly contacts any one of: a ... | 09/06/2011 |
| 7939893 | Semiconductor device and its manufacturing method A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall space... | 05/10/2011 |
| 7888740 | Semiconductor device and method of manufacturing the same The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating fil... | 02/15/2011 |
| 7880235 | Semiconductor integrated circuit device A semiconductor integrated circuit device has an SOI substrate comprising an insulating film laminated on a semiconductor support substrate and a semiconductor thin film laminated on the insulating film. A first N-channel MOS transistor, a first P-channel MOS transi... | 02/01/2011 |
| 7825475 | Mixed voltage tolerant input/output electrostatic discharge devices An input/output (I/O) mixed-voltage drive circuit and electrostatic discharge protection device for coupling to an I/O pad. The device includes an NFET device having a gate, a drain, a source and body, the gate adapted for coupling to a pre-drive circuit, the source... | 11/02/2010 |
| 7808048 | System and method for providing a buried thin film resistor having end caps defined by a dielectric mask A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. A layer of dielectric material is formed over th... | 10/05/2010 |
| 7714390 | Integrated circuit comprising a substrate and a resistor An integrated circuit includes a substrate and a resistor. The resistor is formed from at least two access wells of a first conductivity type and a deep buried layer electrically connecting the wells. The deep buried layer is at least partly covered by a region of o... | 05/11/2010 |
| 7709899 | Semiconductor apparatus A semiconductor apparatus is disclosed. The semiconductor apparatus comprises a substrate with a pad, an internal circuitry region, and a protection resistance formed on the substrate. The pad is connected to a first electrode of the protection resistance by wiring,... | 05/04/2010 |
| 7436223 | Technique for improving negative potential immunity of an integrated circuit An integrated circuit (IC) with negative potential protection includes a switch, a gate drive circuit and a comparator. The switch includes a double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-t... | 10/14/2008 |
| 7420251 | Electrostatic discharge protection circuit and driving circuit for an LCD using the same An exemplary ESD protection circuit includes first and second sets of transistors and an ESD discharge transistor. Each of the transistors includes a source electrode, a drain electrode, and a gate electrode. The drain electrodes and gate electrodes of each of the t... | 09/02/2008 |
| 7402846 | Electrostatic discharge (ESD) protection structure and a circuit using the same An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one bod... | 07/22/2008 |
| 7402871 | Semiconductor device having resistor and method of fabricating the same In a semiconductor device having a resistor and a method of fabricating the same, the device includes a semiconductor substrate having a cell region and a peripheral region. A lower interlayer insulating layer is disposed on the semiconductor substrate. A buffer pad... | 07/22/2008 |
| 7400027 | Nonvolatile memory device having two or more resistance elements and methods of forming and using the same A nonvolatile memory device having two or more resistors and methods of forming and using the same. A nonvolatile memory device having two resistance layers, and more particularly, to a nonvolatile memory device formed and operated using a resistance layer having me... | 07/15/2008 |
| 7397087 | FEOL/MEOL metal resistor for high end CMOS A FEOL/MEOL metal resistor that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors ... | 07/08/2008 |
| 7394134 | Semiconductor device with electrostatic discharge protection A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the int... | 07/01/2008 |
| 7394110 | Planar vertical resistor and bond pad resistor Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In ... | 07/01/2008 |
| 7394156 | Semiconductor integrated circuit device and method of producing the same A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cel... | 07/01/2008 |
| 7391082 | Semiconductor integrated circuit having resistor A semiconductor integrated circuit having a resistor is disclosed in which the resistor is formed by a series connection of one element having a positive temperature coefficient and another element having a negative temperature coefficient. ... | 06/24/2008 |
| 7365397 | Semiconductor device The semiconductor device comprises a resistance element 26 formed of polysilicon film formed on a silicon substrate 10, which includes a resistor part 26a having a resistance value set at a prescribed value, contact parts 26b | 04/29/2008 |
| 7361957 | Device for electrostatic discharge protection and method of manufacturing the same The present invention relates to a device for electrostatic discharge protection (ESD). According to an embodiment of the present invention, a device for electrostatic discharge protection includes a semiconductor substrate, a plurality of field oxide films formed i... | 04/22/2008 |
| 7354813 | Method for electrostatic discharge protection in integrated circuits An output circuit of an integrated circuit device includes first and second MOS transistors including respective spaced apart pairs of source and drain regions in a substrate, arranged such that respective first and second channels of the first and second MOS transi... | 04/08/2008 |
| 7355250 | Electrostatic discharge device with controllable holding current An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept be... | 04/08/2008 |
| 7352199 | Memory card with enhanced testability and methods of making and using the same By decreasing the amount of card substrate required in a memory card to support the actual memory unit, the test interface of the card, which is usually removed before final assembly of the card, can be brought within the allowable length of the finished card and ca... | 04/01/2008 |
| 7342281 | Electrostatic discharge protection circuit using triple welled silicon controlled rectifier Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well cor... | 03/11/2008 |
| 7332748 | Electro-static discharge protection device An electro-static discharge protection device includes a first conductive type well and a second conductive type well which are formed in a surface of the first conductive type layer or a first conductive type substrate. A first high concentration second conductive ... | 02/19/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7325746 | Memory card and semiconductor device An antenna connection function for a noncontact interface is provided by suppressing a modification in a pin arrangement and a pin shape of a memory card that does not correspond to the noncontact interface. Two antenna connecting pins having the memory card are div... | 02/05/2008 |
| 7323753 | MOS transistor circuit and voltage-boosting booster circuit To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on alternately. A pulse is applied to other end of the capacitor which is c... | 01/29/2008 |
| 7319254 | Semiconductor memory device having resistor and method of fabricating the same A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A stor... | 01/15/2008 |
| 7317601 | Electrostatic discharge protection device and circuit thereof An electrostatic discharge (ESD) protection circuit including a detection circuit for detecting the ESD current and a clamp circuit for bypassing an ESD current between a first pad and a second pad is provided. The detection circuit is connected between the first pa... | 01/08/2008 |
| 7317630 | Nonvolatile semiconductor memory apparatus A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, ... | 01/08/2008 |
| 7312967 | Electronic apparatus By voltage limiting means, which provided in an IC as one of the components of an electronic apparatus, and a resistor, which is provided between a voltage input terminal of the IC and an external terminal of the electronic apparatus, an unexpected abnormal voltage ... | 12/25/2007 |
| 7312485 | CMOS fabrication process utilizing special transistor orientation Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the | 12/25/2007 |
| 7304339 | Passivation structure for ferroelectric thin-film devices Ferroelectric thin film devices including a passivation structure to reduce or control a leakage path between two electrodes and along an interface between a ferroelectric thin film layer and a passivation layer are described. Methods for fabricating such devices ar... | 12/04/2007 |
| 7298010 | Radiation-hardened transistor and integrated circuit A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body termi... | 11/20/2007 |
| 7294918 | Memory card with connecting portions for connection to an adapter On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a... | 11/13/2007 |
| 7288820 | Low voltage NMOS-based electrostatic discharge clamp Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current... | 10/30/2007 |
