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"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 8120113 | Metal line in semiconductor device A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches... | 02/21/2012 |
| 8110876 | System for ESD protection with extra headroom in relatively low supply voltage integrated circuits An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to g... | 02/07/2012 |
| 8008724 | Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS tr... | 08/30/2011 |
| 7986011 | Electrostatic discharge protection device The invention provides an electrostatic discharge (ESD) protection device with an increased capability to discharge ESD generated current with a reduced device area. The ESD protection device comprises a grounded gate MOS transistor (1) with a source region (... | 07/26/2011 |
| 7948036 | I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple ga... | 05/24/2011 |
| 7851864 | Test structure of a semiconductor device and semiconductor device A test structure includes a transistor, a dummy transistor and a pad unit. The transistor is formed on a first active region of a substrate. The dummy transistor is formed on a second active region of the substrate and electrically connected to the transistor. The p... | 12/14/2010 |
| 7843010 | Crystalline semiconductor film and method for manufacturing the same An island of a crystalline semiconductor according to the present invention has an upper surface and a sloped side surface, which are joined together with a curved surface. Crystal grains in a body portion of the island, including the upper surface, and crystal grai... | 11/30/2010 |
| 7781841 | System and method to reduce noise in a substrate Certain embodiments of the invention may be found in, for example, a system that reduces noise in a substrate of a chip and may comprise a substrate layer that is integrated within the chip. A transistor layer is integrated within the chip and is shielded from the s... | 08/24/2010 |
| 7741680 | Electro-static discharge and latchup resistant semiconductor device The present invention relates to a semiconductor device including a substrate layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), a backgate region, an isolation layer and a diode. The MOSFET includes a gate region, a source region and a drain regio... | 06/22/2010 |
| 7737500 | CMOS diodes with dual gate conductors, and methods for forming the same The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between th... | 06/15/2010 |
| 7709898 | Semiconductor protection circuit, method for fabricating the same and method for operating semiconductor protection circuit A protection circuit protects a semiconductor device provided on a semiconductor substrate and including an interconnect from charge entering the interconnect during fabrication of the semiconductor device. The protection circuit includes a first metal interconnect ... | 05/04/2010 |
| 7687859 | Electronic circuit and method of manufacturing an electronic circuit An electronic circuit includes at least one field effect transistor that is to be protected against electrostatic discharge events, and at least one protection field effect transistor. The protection field effect transistor has a crystal orientation that is differen... | 03/30/2010 |
| 7642601 | Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell ... | 01/05/2010 |
| 7582938 | I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple ga... | 09/01/2009 |
| 7554158 | Semiconductor device having analog and digital circuits An N-type deep well is used to protect a circuit from a noise. However, a noise with a high frequency propagates through the N-type deep well, and as a result, the circuit that should be protected malfunctions. To reduce the area of the N-type deep well. For instanc... | 06/30/2009 |
| 7545001 | Semiconductor device having high drive current and method of manufacture therefor A semiconductor device including an isolation region located in a substrate, an NMOS device located partially over a surface of the substrate, and a PMOS device isolated from the NMOS device by the isolation region and located partially over the surface. A first one... | 06/09/2009 |
| 7541647 | Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell ... | 06/02/2009 |
| 7476941 | Semiconductor integrated circuit device and fabrication process thereof A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation f... | 01/13/2009 |
| 7456477 | Electrostatic discharge device and method The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current ... | 11/25/2008 |
| 7439590 | Semiconductor device A semiconductor device features connecting gate patterns of all transistors to a N+ or +P junction by the first connected wiring layer to prevent degradation of characteristics of the semiconductor device which results from plasma damages during a process. In order ... | 10/21/2008 |
| 7429774 | Electrostatic discharge (ESD) protection MOS device and ESD circuitry thereof An NMOS device having protection against electrostatic discharge. The NMOS device includes a P-substrate, a P-epitaxial layer overlying the P-substrate, a P-well in the P-epitaxial layer, an N-well in the P-epitaxial layer and encompassing the P-well, an N-Buried La... | 09/30/2008 |
| 7423324 | Double-gate MOS transistor, double-gate CMOS transistor, and method for manufacturing the same In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-sh... | 09/09/2008 |
| 7417303 | System and method for ESD protection An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circu... | 08/26/2008 |
| 7403361 | Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the ... | 07/22/2008 |
| 7402846 | Electrostatic discharge (ESD) protection structure and a circuit using the same An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one bod... | 07/22/2008 |
| 7396709 | Semiconductor device and method for manufacturing the same A semiconductor device includes a thin film transistor including a semiconductor layer that includes a channel region, a source region and a drain region, a gate insulating film provided on the semiconductor layer, and a gate electrode for controlling the conductivi... | 07/08/2008 |
| 7394156 | Semiconductor integrated circuit device and method of producing the same A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cel... | 07/01/2008 |
| 7385253 | Device for electrostatic discharge protection and circuit thereof Disclosed herein are a device for electrostatic protection and circuit thereof. According to the present invention, a device for electrostatic discharge protection comprises first to third wells formed on a semiconductor substrate, a first device, which includes a w... | 06/10/2008 |
| 7365386 | Semiconductor device and method of manufacturing the semiconductor device A semiconductor device having improved reliability is provided. The semiconductor device has a pixel portion. The pixel portion has a TFT and a storage capacitor. The TFT and the storage capacitor has a semiconductor layer which includes first and second regions for... | 04/29/2008 |
| 7361534 | Method for fabricating SOI device A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying the substrate and separated therefrom by a dielectr... | 04/22/2008 |
| 7361957 | Device for electrostatic discharge protection and method of manufacturing the same The present invention relates to a device for electrostatic discharge protection (ESD). According to an embodiment of the present invention, a device for electrostatic discharge protection includes a semiconductor substrate, a plurality of field oxide films formed i... | 04/22/2008 |
| 7358574 | Semiconductor device having silicide-blocking layer and fabrication method thereof A semiconductor device having a silicide-blocking layer is provided. The device includes a field oxide layer defining an active region, source/drain regions in the active region of a substrate, a gate oxide layer and a gate electrode on the substrate between the sou... | 04/15/2008 |
| 7355250 | Electrostatic discharge device with controllable holding current An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept be... | 04/08/2008 |
| 7352547 | Semiconductor integrated circuit device A semiconductor integrated circuit device of the invention includes: a first power supply system including a first circuit connected with a first power supply line; a second power supply system including a second circuit connected with a second power supply line; a ... | 04/01/2008 |
| 7345345 | Semiconductor device A CMOS semiconductor device having a triple well structure which can block latch-up by preventing parasitic thyristors from turning on is offered with reduced layout area. The CMOS semiconductor device includes a P-type silicon substrate, a first and a second deep N... | 03/18/2008 |
| 7335953 | Circuit substrate, electro-optical device, and electronic apparatus The invention provides a circuit substrate including an electrostatic-breakdown-protection circuit efficient for an EL display panel or the like. A substrate includes a common electrode formed on the perimeter of the substrate, multiple terminals formed on the subst... | 02/26/2008 |
| 7323753 | MOS transistor circuit and voltage-boosting booster circuit To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on alternately. A pulse is applied to other end of the capacitor which is c... | 01/29/2008 |
| 7320910 | Semiconductor device Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon sur... | 01/22/2008 |
| 7317633 | Protection of NROM devices from charge damage A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor and an NMOS transistor the PMO... | 01/08/2008 |
| 7315063 | CMOS transistor and method of manufacturing the same A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. T... | 01/01/2008 |
