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| Number | Title | Issue Date |
| 8169027 | Substrate band gap engineered multi-gate pMOS devices A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first ba... | 05/01/2012 |
| 8120111 | Thin film transistor including insulating film and island-shaped semiconductor film An object of the present invention is to provide a method for manufacturing a thin film transistor which enables heat treatment aimed at improving characteristics of a gate insulating film such as lowering of an interface level or reduction in a fixed charge without... | 02/21/2012 |
| 8106459 | FinFETs having dielectric punch-through stoppers A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion ... | 01/31/2012 |
| 7936019 | Nano and MEMS power sources and methods thereof A power source and methods thereof includes a structure comprising one or more p type layers, one or more n type layers, and one or more intrinsic layers and at least one source of radiation is disposed on at least a portion of the structure. Each of the p type laye... | 05/03/2011 |
| 7915684 | Semiconductor device and manufacturing method thereof To provide a structure and a manufacturing method for efficiently forming a transistor to which tensile strain is preferably applied and a transistor to which compressive strain is preferably applied over the same substrate when stress is applied to a semiconductor ... | 03/29/2011 |
| 7880232 | Processes and apparatus having a semiconductor fin A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch can be carried out to expose at least a portion of the sidewall, causing the dielectric hard mask to reced... | 02/01/2011 |
| 7851862 | Method and resultant structure for floating body memory on bulk wafer A method for making floating body memory cells from a bulk substrate. A thin silicon germanium and overlying silicon layers are formed on the bulk substrate. Anchors and a bridge are formed to support the silicon layer when the silicon germanium layer is etched so t... | 12/14/2010 |
| 7847355 | Semiconductor device including transistors with silicided impurity regions A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher... | 12/07/2010 |
| 7795683 | Thin film transistor structure A structure of a thin film transistor and a method for making the same are provided. The structure includes a strip-shaped silicon island, a gate, and a first and second ion doping regions. The strip-shaped silicon island is a thin film region with a predetermined l... | 09/14/2010 |
| 7723791 | Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating laye... | 05/25/2010 |
| 7714388 | Semiconductor memory device and manufacturing method thereof This discloser concerns a semiconductor device including an insulation layer; a FIN-type semiconductor layer provided on the insulation layer and including a floating body region in an electrically floating state and including a source region and a drain region at b... | 05/11/2010 |
| 7709894 | Semiconductor device including a transistor with a gate electrode having a taper portion A method for manufacturing a semiconductor device having a circuit made up by a TFT (Thin Film Transistor) having GOLD (Gate-Drain Overlapped LDD) structure, which an LDD region overlaps which a portion of a gate electrode, wherein the formation of a concentration d... | 05/04/2010 |
| 7692246 | Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement The present invention provides a FinFET transistor arrangement produced using a method with the steps: providing a substrate (106, 108); forming an active region (1) on the substrate a fin-like channel region (113b′; 113bâ... | 04/06/2010 |
| 7687857 | Integrated circuits Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semicondu... | 03/30/2010 |
| 7579656 | Transistor structure for semiconductor device and method of fabricating the same A transistor for a semiconductor device may include a lower semiconductor layer, an active pattern, including a groove region, on the lower semiconductor layer, a gate pattern at least partially overlapping the active pattern including the groove region, and a gate ... | 08/25/2009 |
| 7569886 | Semiconductor device and manufacture method thereof An object is to provide an element structure of a semiconductor device for increasing an etching margin for various etching steps and a method for manufacturing the semiconductor device having the element structure. An island-shaped semiconductor layer is provided o... | 08/04/2009 |
| 7531879 | Method and resultant structure for floating body memory on bulk wafer A method for making floating body memory cells from a bulk substrate. A thin silicon germanium and overlying silicon layers are formed on the bulk substrate. Anchors and a bridge are formed to support the silicon layer when the silicon germanium layer is etched so t... | 05/12/2009 |
| 7525158 | Semiconductor device having pixel electrode and peripheral circuit A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher... | 04/28/2009 |
| 7436033 | Tri-gated molecular field effect transistor and method of fabricating the same A tri-gated molecular field effect transistor includes a gate electrode formed on a substrate and having grooves in a source region, a drain region and a channel region, and at least one molecule inserted between the source and drain electrodes in the channel region... | 10/14/2008 |
| 7423303 | Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating laye... | 09/09/2008 |
| 7423322 | Thin film transistor and method of fabricating the same A bottom gate thin film transistor and method of fabricating the same are disclosed, in which a channel region is crystallized by a super grain silicon (SGS) crystallization method, including: forming a gate electrode and a gate insulating layer on an insulating sub... | 09/09/2008 |
| 7423324 | Double-gate MOS transistor, double-gate CMOS transistor, and method for manufacturing the same In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-sh... | 09/09/2008 |
| 7417286 | Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same are provided. The semiconductor integrated circuit devices include an interlayer insulating layer formed on a semiconductor substrate and a s... | 08/26/2008 |
| 7405982 | Methods to improve the operation of SOI devices According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse t... | 07/29/2008 |
| 7390717 | Trench power MOSFET fabrication using inside/outside spacers A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are for... | 06/24/2008 |
| RE40339 | Silicon-on-insulator chip having an isolation barrier for reliability An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to... | 05/27/2008 |
| 7375396 | Thin film transistor and method of fabricating the same The present invention discloses a thin film transistor and a method of fabricating the same. The thin film transistor includes an insulating substrate; and a semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulator, and a source/drain ... | 05/20/2008 |
| 7372107 | SOI chip with recess-resistant buried insulator and method of manufacturing the same A semiconductor-on-insulator structure includes a substrate and a buried insulator stack overlying the substrate. The buried insulator stack includes a first dielectric layer and a recess-resistant layer overlying the first dielectric layer. A second dielectric laye... | 05/13/2008 |
| 7355247 | Silicon on diamond-like carbon devices Embodiments of the invention provide substrate with an insulator layer on the substrate. The insulator layer may include diamond-like carbon. A device, such a tri-gate transistor may be formed on the diamond-like carbon layer. ... | 04/08/2008 |
| 7348227 | Semiconductor device and manufacturing method thereof A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a ... | 03/25/2008 |
| 7345344 | Embedded substrate interconnect for underside contact to source and drain regions A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such ... | 03/18/2008 |
| 7339235 | Semiconductor device having SOI structure and manufacturing method thereof A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel dire... | 03/04/2008 |
| 7335950 | Semiconductor device and method of making thereof To provide a thin film transistor having a low OFF characteristic and to provide P-channel type and N-channel type thin film transistors where a difference in characteristics of the P-channel type and the N-channel type thin film transistors is corrected, a region | 02/26/2008 |
| 7329924 | Integrated circuits and methods of forming a field effect transistor Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semicondu... | 02/12/2008 |
| 7317227 | Method for forming pattern of stacked film A semiconductor film serving as an active region of a thin film transistor and an upper oxide film protecting the semiconductor film are dry etched to form the active region. In this case, a fluorine-based gas is used as the etching gas, and the etching gas is switc... | 01/08/2008 |
| 7288809 | Flash memory with buried bit lines A memory cell and a method of forming the same are described. The memory cell is formed on a substrate. The memory cell includes a floating gate that is formed at least in part within the substrate. A bit line region is formed within the substrate in proximity to th... | 10/30/2007 |
| 7279374 | Thin film transistor and method of manufacturing the same A method of manufacturing a thin film transistor is disclosed. The method includes forming an amorphous silicon layer and a blocking layer on an insulating substrate, forming a photoresist layer having first and second photoresist patterns on the blocking layer, etc... | 10/09/2007 |
| 7262464 | Semiconductor device with single crystal semiconductor layer(s) bonded to insulating surface of substrate A semiconductor device includes a substrate with an insulating surface and a single crystal semiconductor layer, which is bonded to the insulating surface of the substrate. The device further includes a first insulating layer, which is provided between the insulatin... | 08/28/2007 |
| 7262431 | Semiconductor thin film forming method and semiconductor device A polycrystal thin film forming method comprising the step of forming a semiconductor thin film on a substrate 14, and the step of flowing a heated gas to the semiconductor thin film while an energy beam 38 is being applied to the semiconductor thin fi... | 08/28/2007 |
| 7259428 | Semiconductor device using SOI structure having a triple-well region A semiconductor device includes a support substrate, a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm, a silicon layer provided on the buried insulation film, a MOSFET provided in the silicon layer, and a triple-well regi... | 08/21/2007 |
