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| Number | Title | Issue Date |
| 6690071 | Semiconductor device using junction leak current A first well of a first conductivity type is formed in a partial region of the surface layer of a semiconductor substrate. A MOS transistor is formed in the first well. The MOS transistor has a gate insulating film, a gate electrode, and first and second ... | 02/10/2004 |
| 6683350 | Transistor and method for manufacturing the same In a process for manufacturing a thin film transistor having a semiconductor layer constituting source and drain regions and a channel forming region, by the semiconductor layer being made thinner in the source and drain regions than in the channel formin... | 01/27/2004 |
| 6677190 | Self-aligned body contact in a semiconductor device A method of forming an electrical contact is provided. The method includes forming a gate dielectric layer adjacent a body region of a transistor structure and forming a layer of dielectric material at least partially defining a trench adjacent the body r... | 01/13/2004 |
| 6674127 | Semiconductor integrated circuit A semiconductor integrated circuit includes: a logic circuit section including transistors formed on an SOI substrate; and a partially-depletion-type transistor, which is formed on the SOI substrate as a switching transistor for controlling ON/OFF states ... | 01/06/2004 |
| 6670675 | Deep trench body SOI contacts with epitaxial layer formation A silicon-on-insulation (SOI) body contact is formed within a device region of an SOI substrate so that no space of the SOI substrate is wasted for implementing a body contact. The body contact is formed by epitaxially growing silicon and depositing polys... | 12/30/2003 |
| 6667517 | Electrooptical device and electronic device An electrooptical device including a semiconductor device which is formed in a semiconductor layer on an insulating layer in such a manner that floating substrate effects which are essential in a SOI structure is suppressed without reducing the aperture r... | 12/23/2003 |
| 6657261 | Ground-plane device with back oxide topography A ground-plane SOI device including at least a gate region that is formed on a top Si-containing layer of a SOI wafer, said top Si-containing layer being formed on a non-planar buried oxide layer, wherein said non-planar buried oxide layer has a thickness... | 12/02/2003 |
| 6653670 | Silicon-on-insulator diodes and ESD protection circuits A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN ... | 11/25/2003 |
| 6649944 | Silicon-on-insulator diodes and ESD protection circuits A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, thus providing more junction area than a normal diode. The SOI non-gated junction diode has a PN... | 11/18/2003 |
| 6649455 | SOI type MOS element and manufacturing method thereof To present a SOI type MOS element excellent in yield, performance and characteristic, easy in manufacture, and low in cost, and a method of manufacturing the same. A SOI type MOS transistor structure comprising polysilicon electrodes 128 for gate, source ... | 11/18/2003 |
| 6646308 | Flat panel display device A flat panel display device with improved electrical characteristics and a simplified manufacturing process is disclosed. The device includes a semiconductor layer formed on an insulating substrate; source and drain electrodes directly contacting both end... | 11/11/2003 |
| 6646305 | Grounded body SOI SRAM cell A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a s... | 11/11/2003 |
| 6635909 | Strained fin FETs structure and method A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side o... | 10/21/2003 |
| 6635915 | Semiconductor device having trench capacitor formed in SOI substrate A semiconductor device comprises an SOI substrate, a trench, a trench capacitor, and a conductive layer. The SOI substrate includes a fist semiconductor region, a buried insulating film formed on the first semiconductor region, and a second semiconductor ... | 10/21/2003 |
| 6635518 | SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies Methods and apparatus are provided for creating field effect transistor (FET) body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits. The FET body connections are created ... | 10/21/2003 |
| 6633061 | SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method In a SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method, a multilayer barrier layer with a potential barrier and a diffusion barrier is used to reliably prevent diffusion of impurities between element lay... | 10/14/2003 |
| 6633067 | Compact SOI body contact link A method and structure for a silicon on insulator (SOI) device with a body contact are provided. The body contact is formed by epitaxial growth from a substrate to the body region of the device. The body contact is self-aligned with the gate of the device... | 10/14/2003 |
| 6627952 | Silicon oxide insulator (SOI) semiconductor having selectively linked body A silicon oxide insulator (SOI) device includes an SOI layer supported on a silicon substrate. A body region is disposed on the SOI layer, and the body region is characterized by a first conductivity type. Source and drain regions are juxtaposed with the ... | 09/30/2003 |
| 6624475 | SOI low capacitance body contact An FET device and method of making comprising a first dielectric layer; a substrate layer on the dielectric layer; a channel region of a first conductivity type formed in the substrate layer; a gate formed above the substrate layer over the channel region... | 09/23/2003 |
| 6624476 | Semiconductor-on-insulator (SOI) substrate having selective dopant implant in insulator layer and method of fabricating A semiconductor-on-insulator (SOI) device includes a buried insulator layer and an overlying semiconductor layer. Portions of the insulator layer are doped with the same dopant material, for example boron, as is in corresponding portions of the overlying ... | 09/23/2003 |
| 6621101 | Thin-film transistor The present invention provides, in a TFT, a channel region facing a gate electrode through a gate insulating film, a source electrode connected to the channel region and a drain region connected to the channel region on the side opposite the source region... | 09/16/2003 |
| 6617647 | Insulated gate semiconductor device and method of manufacturing the same Dot-pattern-like impurity regions 104 are artificially and locally formed on a channel forming region 103. The impurity regions 104 restrain the expansion of a drain side depletion layer toward the channel forming region 103 to prevent the short channel e... | 09/09/2003 |
| 6617644 | Semiconductor device and method of manufacturing the same The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second... | 09/09/2003 |
| 6617646 | Reduced substrate capacitance high performance SOI process A silicon on insulator substrate is provided to include the following: a handle wafer; a layer of bonding material; a device wafer, the device wafer including at least one buried impurity region extending from the layer of bonding material upward into the... | 09/09/2003 |
| 6611027 | Protection transistor with improved edge structure A metal-oxide-semiconductor protection transistor is formed in an active region of a semiconductor layer. The active region includes source and drain diffusion layers, which may be partly silicided, and a body region. A gate electrode extends across the a... | 08/26/2003 |
| 6611023 | Field effect transistor with self alligned double gate and method of forming same A fully depleted silicon on insulator (SOI) field effect transistor (FET) includes a gate positioned above a channel region and an aligned back gate positioned below the channel region and the buried oxide later. Alignment of the back gate with the gate i... | 08/26/2003 |
| 6603174 | Semiconductor device and manufacturing method thereof An SOI substrate (30) comprises a buried oxide film (2), an SOI layer (3) formed on a first region (51) of the surface (2S) of the buried oxide film, and a silicon oxide film (8) formed on a second region (52) of the surface (2S). Formed on the peripheral... | 08/05/2003 |
| 6600196 | Thin film transistor, and manufacturing method thereof The present invention relates to minimizing a leakage current in a floating island portion formed in a thin film transistor. More specifically, the present invention is directed to a thin film transistor including: a source electrode 14 and a drain electr... | 07/29/2003 |
| 6597039 | Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof A composite member containing a separation area inside. A mechanical strength of the separation area is non-uniform along a surface of the composite member or along a bonded face. A mechanical strength of a peripheral portion of the separation area is loc... | 07/22/2003 |
| 6593637 | Method for establishing component isolation regions in SOI semiconductor device A method for making an SOI semiconductor device including a silicon substrate includes implanting oxide and Nitrogen into the substrate and then annealing to drive Oxygen and Nitrogen through and below the buried oxide layer. The implanted species interac... | 07/15/2003 |
| 6593615 | Dielectric gap fill process that effectively reduces capacitance between narrow metal lines using HDP-CVD Substrate bombardment during HDP deposition of carbon-doped silicon oxide film results in filling the gaps between metal lines with carbon-doped low k dielectric material. This leads to the placement of low k dielectric between the narrow metal lines whil... | 07/15/2003 |
| 6586803 | Semiconductor device using an SOI substrate A semiconductor device includes an SOI substrate, trench memory cells including trench capacitors formed in the SOI substrate and a mesa or trench isolation region for isolating the trench memory cells. As a result, the trench memory cells are isolated mo... | 07/01/2003 |
| 6583470 | Radiation tolerant back biased CMOS VLSI A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be ... | 06/24/2003 |
| 6573533 | Semiconductor device, semiconductor gate array, electro-optical device, and electronic equipment A structure is provided which suppresses a parasitic bipolar effect without decreasing the breakdown voltage at the junctions between the excessive carrier extracting region and source/drain regions of a MOS transistor for a voltage of approximately 15 vo... | 06/03/2003 |
| 6573197 | Thermally stable poly-Si/high dielectric constant material interfaces The present invention provides a method of fabricating a thermally stable polysilicon/high-k dielectric film stack utilizing a deposition method wherein Si-containing precursor gas which includes silicon and hydrogen is diluted with an inert gas such as H... | 06/03/2003 |
| 6573563 | SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs A silicon-on-insulator (SOI) integrated, circuit is provided. A plurality of transistor active regions and at least one body contact active region are formed on an SOI substrate. A semiconductor residue layer, which is thinner than the transistor active r... | 06/03/2003 |
| 6570183 | Liquid crystal display for preventing galvanic phenomenon A thin film transistor having a source/drain electrode on an insulating substrate is provided with a metal oxide layer interposed between a source/drain electrode and a metal connecting line. The formation of the metal oxide layer prevents the occurrence ... | 05/27/2003 |
| 6566680 | Semiconductor-on-insulator (SOI) tunneling junction transistor A tunneling junction transistor (TJT) device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The TJT... | 05/20/2003 |
| 6566684 | Active matrix circuit having a TFT with pixel electrode as auxiliary capacitor There is provided a combination of doping process and use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain... | 05/20/2003 |
| 6566712 | SOI structure semiconductor device and a fabrication method thereof A SOI structure semiconductor device includes a silicon substrate (1), an insulating oxide layer (2) formed on the silicon substrate (1), a SOI layer (3) formed on the insulating oxide layer (2) a LOCOS oxide layer (4) formed on the insulating oxide layer... | 05/20/2003 |
