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| Number | Title | Issue Date |
| 8067804 | Semiconductor device having an SOI structure, manufacturing method thereof, and memory circuit The present invention provides a semiconductor device capable of suppressing a body floating effect, and a manufacturing method thereof. A semiconductor device having an SOI structure includes a silicon substrate, a buried insulating layer formed on the silicon subs... | 11/29/2011 |
| 8058689 | Techniques to reduce substrate cross talk on mixed signal and RF circuit design An integrated circuit has a buried insulation layer formed over a semiconductor substrate, and a semiconductor mesa formed over the buried insulation layer. A low resistivity guard ring substantially surrounds the semiconductor mesa and is in contact with the semico... | 11/15/2011 |
| 7994575 | Metal-oxide-semiconductor device structures with tailored dopant depth profiles A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ... | 08/09/2011 |
| 7977749 | Semiconductor device with increased channel area A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around ... | 07/12/2011 |
| 7960792 | Non-volatile memory with a stable threshold voltage on SOI substrate A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type d... | 06/14/2011 |
| 7960791 | Dense pitch bulk FinFET process by selective EPI and etch Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate ... | 06/14/2011 |
| 7923782 | Hybrid SOI/bulk semiconductor transistors Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technolog... | 04/12/2011 |
| 7919813 | Method of manufacturing semiconductor device and semiconductor device Disclosed is a semiconductor device of n-type MOSFET structure, which comprises a semiconductor substrate having a device isolation region, diffusion regions formed in the semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a F-con... | 04/05/2011 |
| 7855417 | Non-volatile memory with a stable threshold voltage on SOI substrate A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type d... | 12/21/2010 |
| 7851860 | Techniques to reduce substrate cross talk on mixed signal and RF circuit design An integrated circuit has a buried insulation layer formed over a semiconductor substrate, and a semiconductor mesa formed over the buried insulation layer. A low resistivity guard ring substantially surrounds the semiconductor mesa and is in contact with the semico... | 12/14/2010 |
| 7795681 | Isolated lateral MOSFET in epi-less substrate A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of... | 09/14/2010 |
| 7781838 | Integrated circuit including a body transistor and method An integrated circuit including a floating body transistor and method. One embodiment provides a transistor including a body region formed in a first portion and a first and a second source/drain region formed in a second and a third portion. The body region is form... | 08/24/2010 |
| 7772648 | Performance enhanced silicon-on-insulator technology The present invention includes a silicon-on-insulator (SOI) wafer that enhances certain performance parameters by increasing silicon device layer and insulator layer thicknesses and increasing silicon handle wafer resistivity. By increasing the silicon device layer ... | 08/10/2010 |
| 7723789 | Nonvolatile memory device with nanowire channel and method for fabricating the same A nonvolatile memory device with nanowire channel and a method for fabricating the same are proposed, in which side etching is used to shrink side walls of a side-gate to form a nanowire pattern, thereby fabricating a nanowire channel on the dielectric of the side w... | 05/25/2010 |
| 7701010 | Method of fabricating transistor including buried insulating layer and transistor fabricated using the same In a method of fabricating a transistor including a buried insulating layer and transistor fabricated using the same, the method includes sequentially forming a sacrificial layer and a top semiconductor layer on a single crystalline semiconductor substrate. A gate p... | 04/20/2010 |
| 7646062 | Semiconductor device comprising buried wiring layer A semiconductor device that suppresses partial discharging to a semiconductor substrate caused by local concentration of current. The semiconductor device includes a semiconductor substrate, a gate electrode buried in the semiconductor substrate, a conductor buried ... | 01/12/2010 |
| 7638845 | Semiconductor device with buried conductive layer A semiconductor device includes a first insulator formed at a part under a semiconductor layer, a second insulator formed under the semiconductor layer in an arranged manner avoiding the first insulator and having a relative dielectric constant different from that o... | 12/29/2009 |
| 7622774 | Method of manufacturing semiconductor device and semiconductor device Disclosed is a semiconductor device of n-type MOSFET structure, which comprises a semiconductor substrate having a device isolation region, diffusion regions formed in the semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a F-con... | 11/24/2009 |
| 7598570 | Semiconductor device, SRAM and manufacturing method of semiconductor device A semiconductor device according to the present invention is provided with an SOI substrate, an active region, a first insulating film (complete separation insulating film), a second insulating film (partial separation insulating film), and a contact portion. Here, ... | 10/06/2009 |
| 7582934 | Isolation spacer for thin SOI devices A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor ... | 09/01/2009 |
| 7579655 | Transistor structure having interconnect to side of diffusion and related method A transistor structure is disclosed including at least one transistor including a diffusion and an interconnect electrically connected to a side of the diffusion and a conductor in electrical contact with the interconnect. The low-resistivity local interconnect is a... | 08/25/2009 |
| 7498636 | Semiconductor device and method of manufacturing the same Variations in characteristics of transistors and a deterioration of a gate oxide film are reduced in a WP step. A method of manufacturing a semiconductor device of the present invention includes the steps of providing a SOI substrate having a semiconductor layer for... | 03/03/2009 |
| 7456476 | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pai... | 11/25/2008 |
| 7442958 | Thin film semiconductor device A thin film semiconductor device is provided which includes an insulating substrate, a Si thin film formed over the insulating substrate, and a transistor with the Si thin film as a channel thereof. The Si thin film includes a polycrystal where a plurality of narrow... | 10/28/2008 |
| 7439585 | Silicon-on-insulator device A Silicon on Insulator (SOI) device is disclosed wherein an extension of P-type doping (303) is implanted between the buried oxide layer of the device and the SOI layer. The extension is of a size and shape to permit the source (309) to be biased at a ... | 10/21/2008 |
| 7432552 | Body biasing structure of SOI A body biasing structure of devices connected in series on an SOI substrate is provided. According to some embodiments, the shallow junction of common source/drain regions enables all devices to bias by only one body contact on an SOI substrate like a conventional b... | 10/07/2008 |
| 7423313 | NAND-type semiconductor storage device and method for manufacturing same According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate ... | 09/09/2008 |
| 7423321 | Double gate MOSFET device A method of fabricating a double gate MOSFET device is provided. The present invention overetches a silicon layer overlying a buried oxide layer using a hard mask of cap oxide on the silicon layer as an etching mask. As a result, source, drain and channel regions ar... | 09/09/2008 |
| 7423324 | Double-gate MOS transistor, double-gate CMOS transistor, and method for manufacturing the same In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-sh... | 09/09/2008 |
| 7420249 | Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insula... | 09/02/2008 |
| 7414289 | SOI Device with charging protection and methods of making same The present invention is directed to an SOI device with charging protection and methods of making the same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device i... | 08/19/2008 |
| 7394130 | Transistor and method for manufacturing the same In a process for manufacturing a thin film transistor having a semiconductor layer constituting source and drain regions and a channel forming region, by the semiconductor layer being made thinner in the source and drain regions than in the channel forming region a ... | 07/01/2008 |
| 7382024 | Low threshold voltage PMOS apparatus and method of fabricating the same A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter... | 06/03/2008 |
| RE40339 | Silicon-on-insulator chip having an isolation barrier for reliability An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to... | 05/27/2008 |
| 7372106 | Semiconductor device and method for manufacturing semiconductor device A semiconductor device comprising electric field relieving regions 8a and 8b for alleviating the electric fields between a source layer 6a and body-source connection layers 7a and 7b formed along ... | 05/13/2008 |
| 7368374 | Super high density module with integrated wafer level packages A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packa... | 05/06/2008 |
| 7365398 | Compact SRAMs and other multiple transistor structures A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one ... | 04/29/2008 |
| 7361534 | Method for fabricating SOI device A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying the substrate and separated therefrom by a dielectr... | 04/22/2008 |
| 7358569 | Semiconductor device with semiconductor layer having various thickness An SOI layer is provided in a buried oxide film and a source and a drain are provided on the upper surface of the SOI layer so that they are kept from contact with the buried oxide film. A depletion layer formed by the source, the drain, and the SOI layer extends to... | 04/15/2008 |
| 7358161 | Methods of forming transistor devices associated with semiconductor-on-insulator constructions The invention encompasses a method of forming a semiconductor on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is fo... | 04/15/2008 |
