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| Number | Title | Issue Date |
| 8183633 | Semiconductor device and method for forming the same Provided is a semiconductor and a method for forming the same. The method includes forming a buried insulating layer locally in a substrate. The substrate is etched to form an opening exposing the buried insulating layer, and a silicon pattern spaced in at least one... | 05/22/2012 |
| 8174073 | Integrated circuit structures with multiple FinFETs A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and s... | 05/08/2012 |
| 8174074 | Asymmetric embedded silicon germanium field effect transistor A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source reg... | 05/08/2012 |
| 8169024 | Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantation A method of fabricating a semiconductor device is provided in which the channel of the device is present in an extremely thin silicon on insulator (ETSOI) layer, i.e., a silicon containing layer having a thickness of less than 10.0 nm. In one embodiment, the method ... | 05/01/2012 |
| 8164143 | Semiconductor device A method for fabricating a semiconductor device comprises: performing a thermal process to expanding a local doped region formed between gate patterns on a semiconductor substrate; and etching a central region of an expanded local doped region so that the expanded l... | 04/24/2012 |
| 8159030 | Strained MOS device and methods for its fabrication An MOS device having enhanced mobility and a method for its fabrication are provided. The method comprises providing a P-type monocrystalline silicon germanium substrate having a first lattice constant and a channel region at the substrate surface, forming a gate in... | 04/17/2012 |
| 8159031 | SOI substrates and SOI devices, and methods for forming the same An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any... | 04/17/2012 |
| 8154080 | Dielectric structure having lower-k and higher-k materials An electronic device including in any sequence: (a) a semiconductor layer; and (b) a dielectric structure comprising a lower-k dielectric polymer and a higher-k dielectric polymer, wherein the lower-k dielectric polymer is in a lower concentration than the higher-k ... | 04/10/2012 |
| 8154081 | Processes and apparatus having a semiconductor fin A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch can be carried out to expose at least a portion of the sidewall, causing the dielectric hard mask to reced... | 04/10/2012 |
| 8148779 | Thin film transistor, method of manufacturing the same and flat panel display device having the same A thin film transistor (TFT) using an oxide semiconductor as an active layer, a method of manufacturing the TFT, and a flat panel display device having the TFT include a gate electrode formed on a substrate; an active layer made of an oxide semiconductor and insulat... | 04/03/2012 |
| 8148780 | Devices and systems relating to a memory cell having a floating body Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first ... | 04/03/2012 |
| 8138546 | Electrostatic discharge protection device and method of fabricating same A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried ox... | 03/20/2012 |
| 8138547 | MOSFET on silicon-on-insulator REDX with asymmetric source-drain contacts A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a ... | 03/20/2012 |
| 8138548 | Thin film transistor array substrate and method for manufacturing the same A thin film transistor array substrate includes a substrate, a gate layer, a gate insulating layer, a source/drain layer, a patterned protective layer, an oxide semiconductor layer, a resin layer and a pixel electrode. The gate layer is disposed on the substrate. Th... | 03/20/2012 |
| 8134208 | Semiconductor device having decreased contact resistance Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to th... | 03/13/2012 |
| 8134209 | Semiconductor device and method for manufacturing the same Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench re... | 03/13/2012 |
| 8129787 | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby ... | 03/06/2012 |
| 8125032 | Modified hybrid orientation technology A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the seco... | 02/28/2012 |
| 8115254 | Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI... | 02/14/2012 |
| 8115255 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device comprises including a insulating pattern and a silicon film over a SOI substrate, thereby increasing a reduced volume of a floating body after forming a floating body fin transistor so as to secure a data storage spa... | 02/14/2012 |
| 8106456 | SOI transistors having an embedded extension region to improve extension resistance and channel strain characteristics A silicon-on-insulator (SOI) transistor device includes a buried insulator layer formed over a bulk substrate; an SOI layer formed on the buried insulator layer; and a pair of silicon containing epitaxial regions disposed adjacent opposing sides of a gate conductor,... | 01/31/2012 |
| 8106455 | Threshold voltage adjustment through gate dielectric stack modification Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in oth... | 01/31/2012 |
| 8101999 | SOI substrate and method for producing the same, solid-state image pickup device and method for producing the same, and image pickup apparatus A SOI substrate includes a silicon substrate, a silicon oxide layer arranged on the silicon substrate, a silicon layer arranged on the silicon oxide layer, a gettering layer arranged in the silicon substrate, and a damaged layer formed of an impurity-doped region ar... | 01/24/2012 |
| 8101998 | MOSFET and manufacturing method thereof The present invention provides a MOSFET capable of improving the basic performance of a transistor such as saturation current characteristics, input follow-up and an offleak current at high levels, and a manufacturing method thereof. The MOSFET comprises a semicondu... | 01/24/2012 |
| 8089125 | Integrated circuit system with triode An integrated circuit system includes an integrated circuit, forming a triode near the integrated circuit, and attaching a connector to the triode and the integrated circuit. ... | 01/03/2012 |
| 8089126 | Method and structures for improving substrate loss and linearity in SOI substrates Methods and structures for improving substrate loss and linearity in SOI substrates. The methods include forming damaged crystal structure regions under the buried oxide layer of SOI substrates and the structures included damaged crystal structure regions under the ... | 01/03/2012 |
| 8084818 | High mobility tri-gate devices and methods of fabrication A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a crystal plane location on the first substrate and a second substrate formed o... | 12/27/2011 |
| 8084819 | Semiconductor memory device having insulation patterns and cell gate patterns Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through t... | 12/27/2011 |
| 8080850 | Semiconductor device having semiconductor layer on insulating structure and method of manufacturing the same A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity cont... | 12/20/2011 |
| 8080849 | Characterizing films using optical filter pseudo substrate A system and method of characterizing a parameter of an ultra thin film, such as a gate oxide layer. A system is disclosed that includes a structure having a pseudo substrate positioned below an ultra thin film, wherein the pseudo substrate includes an optical mirro... | 12/20/2011 |
| 8076727 | Magnesium-doped zinc oxide structures and methods Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resul... | 12/13/2011 |
| 8067803 | Memory devices, transistor devices and related methods A memory device and method of making the memory device. The memory device comprises a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are ... | 11/29/2011 |
| 8067802 | Flexible device and method of manufacturing the same The rollable device of the invention comprises a substrate of an insulating material (12) with apertures (15) extending from a first to a second side. On the first side switching elements (13) are present, as well as interconnect lines and the l... | 11/29/2011 |
| 8053839 | Doping of semiconductor fin devices A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surfac... | 11/08/2011 |
| 8053837 | Semiconductor device There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut ... | 11/08/2011 |
| 8053838 | Structures, fabrication methods, design structures for strained fin field effect transistors (FinFets) A semiconductor structure, a fabrication method, and a design structure for a FinFet. The FinFet includes a dielectric layer, a central semiconductor fin region on the dielectric layer, a first semiconductor seed region on the dielectric layer, and a first strain cr... | 11/08/2011 |
| 8049277 | Epitaxy silicon on insulator (ESOI) Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI s... | 11/01/2011 |
| 8030707 | Semiconductor structure A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes ... | 10/04/2011 |
| 8022478 | Method of forming a multi-fin multi-gate field effect transistor with tailored drive current Disclosed are embodiments of an improved multi-gated field effect transistor (MUGFET) structure and method of forming the MUGFET structure so that it exhibits a more tailored drive current. Specifically, the MUGFET incorporates multiple semiconductor fins in order t... | 09/20/2011 |
| 8017998 | Gettering contaminants for integrated circuits formed on a silicon-on-insulator structure Gettering contaminants for formation of integrated circuits on a semiconductor-on-insulator structure is described. A semiconductor-on-insulator structure is configured to attract contaminants. Contaminant attractor regions are formed using ion implantation into a s... | 09/13/2011 |
