Class 257/344 - With lightly doped portion of drain region adjacent channel (e.g., LDD structure)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein the short channel IGFET has a lightly
No. of patents: 1175
Last issue date: 04/24/2012

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Number	Title	Issue Date
6979879	Trim zener using double poly process In a zener zap diode device and a system for making such a device using a double poly process, p+ and n+regions are formed in a tub by means of p-doped and n-doped polysilicon regions, and a p-n junction is formed between the p+ region and an n-tub or between the n+...	12/27/2005
6979885	Devices with patterned wells and method for forming same In a semiconductor substrate with a top surface, a PN junction between a first region of one conductivity type formed by masked diffusion into a semiconductor from the surface and a second region of opposite conductivity type formed into a first portion of the first...	12/27/2005
6979658	Method of fabricating a semiconductor device containing nitrogen in a gate oxide film A semiconductor device includes a substrate, a gate oxide film formed on the substrate, a gate electrode provided on the gate oxide film, first and second diffusion regions formed in the substrate at both lateral sides of the gate electrode. The gate electrode inclu...	12/27/2005
6977419	MOSFETs including a dielectric plug to suppress short-channel effects The invention provides a technique to fabricate a dielectric plug in a MOSFET. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source a...	12/20/2005
6977392	Semiconductor display device An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudina...	12/20/2005
6977393	Electro-optical device and manufacturing method thereof A semiconductor device that uses a high reliability TFT structure is provided. The gate electrode of an n-channel type TFT is formed by a first gate electrode and a second gate electrode that covers the first gate electrode. LDD regions have portions that overlap th...	12/20/2005
6977417	Semiconductor device and method of fabricating the same An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gat...	12/20/2005
6974998	Field effect transistor with corner diffusions for reduced leakage The present invention includes an advanced MOSFET design and manufacturing approach that allow further increase in IC packing density by appropriately addressing the increased leakage problems associated with it. The MOSFET according to one embodiment of the present...	12/13/2005
6974999	Semiconductor device and method of manufacturing the same It is an object to suppress a change in a characteristic of a semiconductor device with a removal of a hard mask while making the most of an advantage of a gate electrode formed by using the hard mask. A gate electrode (3) is formed by etching using a hard ma...	12/13/2005
6975000	Method of forming a recessed buried-diffusion device A method of forming a device (and the device so formed) comprising the following steps. A structure having a gate structure formed thereover is provided. Respective low doped drains are formed within the structure at least adjacent to the gate structure. A pocket im...	12/13/2005
6975015	Modulated trigger device An integrated circuit structure, a trigger device and a method of electrostatic discharge protection, the integrated circuit structure including: a substrate having a top surface defining a horizontal direction, the substrate of a first dopant type; a first horizont...	12/13/2005
6974997	High-voltage MOS transistor A high-voltage MOS transistor capable of lowering the maximum substrate current without sacrificing the driving capacity of the transistor itself, and ensuring an acceptable lifetime of hot carriers is provided. By providing an overlapping region in a boundary regio...	12/13/2005
6972463	Multi-finger transistor A multi-finger transistor is described, including multiple parallel transistors. Each transistor includes a gate dielectric layer, a gate, a source/drain region, and a drift region in the peripheral substrate of the source/drain region separating the source/drain re...	12/06/2005
6972234	High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage A method of fabricating CMOS devices suitable for high voltage and low voltage applications, while maintaining minimum channel lengths for the devices. In one embodiment, pocket implants (310) are formed in a minimum channel device causing a reverse channel e...	12/06/2005
6969646	Method of activating polysilicon gate structure dopants after offset spacer deposition A process sequence used to integrate an anneal cycle, used to activate ion implanted dopants in a polysilicon gate structure, and the definition of offset silicon oxide spacers on the sides of the polysilicon gate structure, has been developed. The process sequence ...	11/29/2005
6967143	Semiconductor fabrication process with asymmetrical conductive spacers A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that ...	11/22/2005
6967380	CMOS device having retrograde n-well and p-well A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs ...	11/22/2005
6965151	Device including a resistive path to introduce an equivalent RC circuit Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the dev...	11/15/2005
6962862	Manufacturing method of semiconductor device A method of manufacturing a semiconductor device having an isolation region, a trench formed on a semiconductor substrate and an insulating film buried within the trench; includes: forming a gate electrode in an active region adjacent to the isolation region; applyi...	11/08/2005
6963114	SOI MOSFET with multi-sided source/drain silicide A microelectronic device including an insulator located over a substrate, a semiconductor feature and a contact layer. The semiconductor feature has a thickness over the insulator, a first surface opposite the insulator, and a sidewall spanning at least a portion of...	11/08/2005
6963109	Semiconductor device and method for manufacturing the same A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate electrode. A second low concentration (SLN type) drain region is for...	11/08/2005
6960807	Drain extend MOS transistor with improved breakdown robustness A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions (	11/01/2005
6960517	N-gate transistor A n-gate transistor, and method of forming such, including source/drain regions connected by a channel region and a gate electrode coupled to the channel region. The channel region has many angled edges protruding into the gate electrode. The many angled edges are t...	11/01/2005
6958518	Semiconductor device having at least one source/drain region formed on an isolation region and a method of manufacture therefor The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a semiconductor substrate having a gate formed there over. The semiconductor device further includes an isolation region having at least one...	10/25/2005
6956263	Field effect transistor structure with self-aligned raised source/drain extensions Field effect transistor structures include a channel region formed in a recessed portion of a substrate. The recessed channel portion permits the use of relatively thicker source/drain regions thereby providing lower source/drain extension resistivity while maintain...	10/18/2005
6956276	Semiconductor device with an L-shaped/reversed L-shaped gate side-wall insulating film Provided is a semiconductor device, comprising a gate electrode formed on a semiconductor substrate, source/drain diffusion layers formed on both sides of the gate electrode, a gate electrode side-wall on the side of the source/drain diffusion layer and a gate side-...	10/18/2005
6953730	Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from alloys such as cobalt-titanium are thermodynamically stable s...	10/11/2005
6951793	Low-temperature polysilicon thin film transistor having buried LDD structure and process for producing same A low-temperature polysilicon thin film transistor having a buried LDD structure is provided. Two heavily doped regions are formed in a semiconductor layer and distributed just below a surface of the semiconductor layer. Two LDD regions are both sandwiched between t...	10/04/2005
6952040	Transistor structure and method of fabrication A novel transistor structure and its method of fabrication. According to the present invention, the transistor includes an intrinsic silicon body having a first surface. A gate dielectric is formed on the first surface of the intrinsic silicon body. A gate electrode...	10/04/2005
6951785	Methods of forming field effect transistors including raised source/drain regions A method of forming a field effect transistor may include forming a doped layer at a surface of a semiconductor substrate, and forming a groove through the doped layer at the surface of the semiconductor substrate while maintaining portions of the doped layer on opp...	10/04/2005
6952020	Semiconductor device and manufacturing method thereof A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at l...	10/04/2005
6952036	Thin-film transistor structure, method for manufacturing the thin-film transistor structure, and display device using the thin-film transistor structure The present invention provides a thin film transistor structure in which at least a trench is formed in an insulating polymer film formed on a substrate. In the thin film transistor structure, a trench formed in the insulating polymer film accommodates a gate wiring...	10/04/2005
6949796	Halo implant in semiconductor structures A halo implant method for forming halo regions of at least first and second transistors formed on a same semiconductor substrate. The first transistor comprises a first gate region disposed between first and second semiconductor regions. The second transistor compri...	09/27/2005
6949421	Method of forming a vertical MOS transistor A vertical MOS transistor has a very short channel length that is indirectly defined by the thickness of a layer of semiconductor material or the depths of implants. The transistor has a first (source/drain) region formed in a substrate material, a semiconductor reg...	09/27/2005
6943077	Selective spacer layer deposition method for forming spacers with different widths A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer...	09/13/2005
6939770	Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabricatio...	09/06/2005
6940124	Semiconductor device and manufacturing method thereof Channel doping is an effective method for controlling Vth, but if Vth shifts to the order of −4 to −3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is dif...	09/06/2005
6939750	Thin film transistor device and method of manufacturing the same A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are form...	09/06/2005
6936848	Dual gate layout for thin film transistor A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a...	08/30/2005
6933561	Semiconductor device and method of manufacturing the same A semiconductor device includes a post-oxide film comprising first, second and third portions. The first portion extends on the sidewall of a gate electrode provided on a gate insulating film on the surface of the semiconductor substrate to the surface of the semico...	08/23/2005

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Class 257/344 - With lightly doped portion of drain region adjacent channel (e.g., LDD structure)