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| Number | Title | Issue Date |
| 4514897 | Electrically programmable floating gate semiconductor memory device An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the s... | 05/07/1985 |
| 4488351 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device, capable of forming, with good controllability, impurity regions of a low impurity concentration, includes the steps of: forming a gate electrode on a surface of a semiconductor substrate through a gate ox... | 12/18/1984 |
| 4419810 | Self-aligned field effect transistor process A method for fabricating a semiconductor [integrated circuit] structure having a sub-micrometer gate length field effect transistor device is described. An isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconducto... | 12/13/1983 |
| 4419809 | Fabrication process of sub-micrometer channel length MOSFETs Methods for fabricating a semiconductor integrated circuit having a sub-micrometer gate length field effect transistor devices are described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semicondu... | 12/13/1983 |
| 4406049 | Very high density cells comprising a ROM and method of manufacturing same The subject invention conserves memory real estate by employing ROM cells which are FETs or non-FETs depending upon the programming. Each cell comprises a gate, a source and drain region and provision for connections to bit and word lines. Programming is ... | 09/27/1983 |
| 4404733 | Method of producing semiconductor devices An improved contact hole in a method of producing a semiconductor device by forming a silicon dioxide insulating layer by a chemical vapor deposition method on a semiconductor substrate, forming a contact hole in the insulating layer diffusing phosphorus ... | 09/20/1983 |
| 4402761 | Method of making self-aligned gate MOS device having small channel lengths A semiconductor structure wherein a masking layer is formed to cover a portion of a surface of a semiconductor. A first doped region is formed in a portion of the semiconductor exposed by the masking layer. A chemical etchant is brought into contact with ... | 09/06/1983 |
| 4366613 | Method of fabricating an MOS dynamic RAM with lightly doped drain A method of manufacturing LDD MOS FET RAM capable of delineating short (less than 1 micrometer) lightly doped drain regions. An N- implant is effected between gate electrodes and field oxide insulators, before the N+ implant. An insu... | 01/04/1983 |
| 4356623 | Fabrication of submicron semiconductor devices A method for fabricating a semiconductor device of relatively small scale. A conductivity layer is deposited on a substrate of a polarity. Regions of opposite polarity are partially formed on either side of the conductor layer. Vertical layers are formed ... | 11/02/1982 |
| 4334235 | Insulated gate type semiconductor device In an insulated-gate type static induction transistor having a source region for supplying charge carriers, a channel region through which said carriers travel, an insulated electrode type gate structure to which is inputted a gate voltage for controlling... | 06/08/1982 |
| 4199733 | Extended-drain MOS mirrors An improved current amplifier, of the type having input, output and common terminals and which is subject to having widely dissimilar voltages at its input and output terminals has field-effect master and slave transistors formed in a region of semiconduc... | 04/22/1980 |
| 4154626 | Process of making field effect transistor having improved threshold stability by ion-implantation An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a ... | 05/15/1979 |
| 4080618 | Insulated-gate field-effect transistor An insulated-gate field-effect transistor having improved high-speed operation characteristics and high channel controllability includes a source region having first and second diffused regions and a drain region having first and second diffused regions. ... | 03/21/1978 |
| 3933529 | Process for the production of a pair of complementary field effect transistors A process for the production of a pair of complementary field effect transistors which have very short channel lengths. A lightly doped semiconductor layer is deposited on an electrically insulating substrate. A gate insulator layer is applied onto which ... | 01/20/1976 |
