Did You Know...
...that the x-ray was discovered purely by accident? When German physicist Wilhelm Konrad von Roentgen was experimenting with cathode rays in 1895, he put an activated Crookes tube in a book and went out to lunch. When he returned, he discovered that a key that had also been placed in the book showed up as an image on the developed film!
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| Number | Title | Issue Date |
| 7315174 | Method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device A method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device is disclosed. According to the method of measuring flat-band status capacitance of gate oxide in MOS transistor device, flat-band status capacitance of gate oxide in MOS tr... | 01/01/2008 |
| 7315466 | Semiconductor memory device and method for arranging and manufacturing the same A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input ... | 01/01/2008 |
| 7312500 | Manufacturing method of semiconductor device suppressing short-channel effect An ideal step-profile in a channel region is realized easily and reliably, whereby suppression of the short-channel effect and prevention of mobility degradation are achieved together. A silicon substrate is amorphized to a predetermined depth from a semiconductor f... | 12/25/2007 |
| 7310268 | Float gate memory device A float gate memory device comprises a bottom word line, a float channel layer formed on the bottom word line and kept at a floating state, a float gate, and a top word line formed on the float gate in parallel with the bottom word line. In the float gate formed on ... | 12/18/2007 |
| 7304350 | Threshold voltage control layer in a semiconductor device A semiconductor device has a well region having a first conductivity type and formed in an upper portion of a semiconductor substrate, a gate insulating film and a gate electrode formed successively on the well region of the semiconductor substrate, a threshold volt... | 12/04/2007 |
| 7301219 | Electrically erasable programmable read only memory (EEPROM) cell and method for making the same An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to th... | 11/27/2007 |
| 7294573 | Method for controlling poly 1 thickness and uniformity in a memory array fabrication process According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surface... | 11/13/2007 |
| 7288814 | Selective post-doping of gate structures by means of selective oxide growth A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spac... | 10/30/2007 |
| 7288817 | Reverse metal process for creating a metal silicide transistor gate structure The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate co... | 10/30/2007 |
| 7279399 | Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/09/2007 |
| 7279758 | N-channel MOSFETs comprising dual stressors, and methods for forming the same The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single... | 10/09/2007 |
| 7279741 | Semiconductor device with increased effective channel length and method of manufacturing the same A semiconductor device with an increased effective channel length and a method of manufacturing the same. The device includes a semiconductor substrate, a gate insulating layer disposed on the semiconductor substrate, a gate electrode structure disposed on a predete... | 10/09/2007 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7279711 | Ferroelectric liquid crystal and goggle type display devices The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode ... | 10/09/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7274056 | Semiconductor constructions The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. Th... | 09/25/2007 |
| 7271436 | Flash memory devices including a pass transistor Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor... | 09/18/2007 |
| 7271443 | Semiconductor device and manufacturing method for the same A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region inclu... | 09/18/2007 |
| 7271403 | Isolating phase change memory devices A phase change memory may be made using an isolation diode in the form of a Schottky diode between a memory cell and a word line. The use of Schottky diode isolation devices may make the memory more scaleable in some embodiments. ... | 09/18/2007 |
| 7268993 | Integrated protector and splitter A method and five pin integrated protector and splitter module are provided for use at a protector panel of a facility for housing telephone-related equipment, where the module is capable of being used in conjunction with at least a broadband MODEM separate from a d... | 09/11/2007 |
| 7268393 | Semiconductor devices and methods of manufacturing the same Semiconductor devices and methods of manufacturing semiconductor devices which achieve higher integration and higher operating speed are provided. A disclosed example semiconductor device includes a semiconductor substrate of a first conductivity type; a gate insula... | 09/11/2007 |
| 7265434 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 09/04/2007 |
| 7265384 | Thin film transistor and organic electroluminescence display using the same A thin film transistor (TFT) having a lightly doped drain (LDD) structure includes a lightly doped drain (LDD) region formation pattern, an active layer formed in an uneven structure on the LDD region formation pattern, and having a source region and a drain region ... | 09/04/2007 |
| 7259427 | Semiconductor device and method of manufacturing the same The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode ... | 08/21/2007 |
| 7259432 | Semiconductor device for reducing parasitic capacitance produced in the vicinity of a transistor located within the semiconductor device A semiconductor device includes: a gate electrode formed on a substrate; impurity regions formed in the substrate and to both sides of the gate electrode; a first interlayer insulating film formed to cover the gate electrode; and a second interlayer insulating film ... | 08/21/2007 |
| 7259053 | Methods for forming a device isolation structure in a semiconductor device Methods of forming a device isolation structure in a semiconductor device are disclosed. A disclosed method comprises forming a p-type well and an n-type well in a semiconductor substrate; sequentially depositing a gate insulating layer and a gate electrode material... | 08/21/2007 |
| 7259411 | Vertical MOS transistor A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. Th... | 08/21/2007 |
| 7253481 | High performance MOS device with graded silicide A semiconductor device suffering fewer current crowding effects and a method of forming the same are provided. The semiconductor device includes a substrate, a gate over the substrate, a gate spacer along an edge of the gate and overlying a portion of the substrate,... | 08/07/2007 |
| 7253478 | Semiconductor device The semiconductor device comprises: a semiconductor substrate (N+ substrate 110) containing a first conductivity type impurity implanted therein; a second conductivity type impurity-implanted layer (P+ implanted layer 114) at rela... | 08/07/2007 |
| 7253048 | Method of manufacturing a semiconductor integrated circuit and semiconductor integrated circuit A semiconductor integrated circuit has a CMOS transistor formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film. Thermal oxidation is conducted to form a LOCOS for element... | 08/07/2007 |
| 7253482 | Structure for reducing overlap capacitance in field effect transistors A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extend... | 08/07/2007 |
| 7253062 | Semiconductor device with asymmetric pocket implants A semiconductor device (1) has a source (2) a gate (3) and a drain (4), a single deep-pocket ion implant (8) in a source-drain depletion region, and a single shallow-pocket ion implant (9) in the source-drain depletion regio... | 08/07/2007 |
| 7250647 | Asymmetrical transistor for imager device An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e, one-sided) active area extension region on one side of the transistor gate opposite the pho... | 07/31/2007 |
| 7250661 | Semiconductor memory device with plural source/drain regions A semiconductor memory device includes first and second source/drain regions, and first and second semiconductor regions. The first source/drain region of a first conductive type is formed in a first well region of a second conductive type for a pair of first MIS-ty... | 07/31/2007 |
| 7247534 | Silicon device on Si:C-OI and SGOI and method of manufacture A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second mat... | 07/24/2007 |
| 7247541 | Method of manufacturing a semiconductor memory device including a transistor A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impuri... | 07/24/2007 |
| 7247883 | Thin film transistor having LDD structure A thin film transistor having a LDD structure that may improve its channel reliability and output characteristics. A semiconductor layer comprises source/drain regions, a channel region positioned between the source/drain regions, and an LDD region positioned betwee... | 07/24/2007 |
| 7247919 | Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxides MOSFETs An integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region and a gate oxide layer is provided on the active regions. A gate electrode i... | 07/24/2007 |
| 7244962 | Method of manufacturing semiconductor devices Subjected to obtain a crystalline TFT which simultaneously prevents increase of OFF current and deterioration of ON current. A gate electrode of a crystalline TFT is comprised of a first gate electrode and a second gate electrode formed in contact with the first gat... | 07/17/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
