Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Number | Title | Issue Date |
| 6885066 | SOI type MOSFET A buried insulating film is formed in an LDD region between a source region and a drain region, and a non-doped silicon film is formed in the SOI layer above the buried insulating film. The SOI layer lying under the buried insulating film has a body concentration of... | 04/26/2005 |
| 6881630 | Methods for fabricating field effect transistors having elevated source/drain regions Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposi... | 04/19/2005 |
| 6882013 | Transistor with reduced short channel effects and method A method of fabricating a transistor (10) comprises forming source and drain regions (46) and (47) using a first sidewall (42) and (43) as a mask and forming a deep blanket source and drain regions (54) and (56) using... | 04/19/2005 |
| 6876037 | Fully-depleted SOI device The present invention is generally directed to a fully-depleted SOI device structure. In one illustrative embodiment, the device comprises first, second and third doped regions formed in the bulk substrate, wherein the dopant concentration level in the doped regions... | 04/05/2005 |
| 6873011 | High voltage and low on-resistance LDMOS transistor having equalized capacitance A high voltage LDMOS transistor according to the present invention includes P-field blocks in the extended drain region of a N-well. The P-field blocks form the junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain re... | 03/29/2005 |
| 6870233 | Multi-bit ROM cell with bi-directional read and a method for making thereof A multi-bit Read Only Memory (ROM) cell has a semiconductor substrate of a first conductivity type with a first concentration. A first and second regions of a second conductivity type spaced apart from one another are in the substrate. A channel is between the first... | 03/22/2005 |
| 6870219 | Field effect transistor and method of manufacturing same A field effect transistor includes a drain region (12) having a first portion (18) and a second portion (20), with the second portion being more lightly doped than the first portion. A channel region (14) is adjacent to the second portion... | 03/22/2005 |
| 6867458 | Semiconductor device and method for fabricating the same Provided is a semiconductor device having a source region formed of a semiconductor, a drain region formed of a semiconductor of the same conductive type as that of the source region, a channel region formed of a semiconductor between the source region and the drain... | 03/15/2005 |
| 6864533 | MOS field effect transistor with reduced on-resistance A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions ar... | 03/08/2005 |
| 6861704 | Semiconductor device and method for fabricating the same The semiconductor device comprises a gate electrode 26 formed on a semiconductor substrate 10, a source region 45a having a lightly doped source region 42a and a heavily doped source region 44a, a drain region ... | 03/01/2005 |
| 6861684 | Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor The vertical transistor includes, on a semiconductor substrate, a vertical pillar 5 having one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielect... | 03/01/2005 |
| 6861318 | Semiconductor transistor having a stressed channel A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium.... | 03/01/2005 |
| 6847080 | Semiconductor device with high and low breakdown voltage and its manufacturing method The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistor... | 01/25/2005 |
| 6841826 | Low-GIDL MOSFET structure and method for fabrication A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing... | 01/11/2005 |
| 6838777 | Semiconductor device and method of manufacturing the same Gate electrodes (3) are formed on a semiconductor substrate (1), each with a gate insulating film (2) interposed therebetween. A pair of offset spacers (4) are respectively formed on opposite side faces of each of the gate insulating film... | 01/04/2005 |
| 6838732 | Semiconductor device and method for manufacturing the same To provide a semiconductor device with reduced parasitic capacity in the vicinity of gate electrodes, and a method for manufacturing such a semiconductor device. The semiconductor device comprises a gate electrode formed on a silicon semiconductor substrate 1 | 01/04/2005 |
| 6835982 | Semiconductor devices A SOI MOSFET 10 may be formed from silicon single crystal as a substrate body that is formed on an embedded oxide film 11. For example, a P-type body 12, a channel section 13, and N-type source region 14 and drain region 15 ... | 12/28/2004 |
| 6835624 | Semiconductor device for protecting electrostatic discharge and method of fabricating the same In a semiconductor device for protecting an electrostatic discharge and a method of fabricating the same, a gate electrode is disposed on a semiconductor substrate of first conductivity type, and a heavily doped region and a vertical lightly doped region surround th... | 12/28/2004 |
| 6831332 | Microwave field effect transistor structure A microwave transistor structure comprising: (1) a substrate having a top surface; (2) a silicon semiconductor material of a first conductivity type; (3) a conductive gate; (4) a channel region of a second conductivity type; (5) a drain region of the second conducti... | 12/14/2004 |
| 6830978 | Semiconductor device and manufacturing method for the same On a semiconductor substrate having a gate electrode and an LDD layer formed thereon, an SiN film to be a silicide block is formed. An opening communicating with the LDD layer is provided for the SiN film. Impurities are introduced into the LDD layer through the ope... | 12/14/2004 |
| 6828629 | Semiconductor device and method of fabricating the same A P-type pocket layer is formed in the surficial portion of a semiconductor substrate, a sidewall insulating film having a thickness of as thin as 10 nm or around is formed, and P is implanted therethrough to thereby form an N-type extension layer in the surficial p... | 12/07/2004 |
| 6828585 | Thin-film transistor, method for fabricating the same, and liquid crystal display device A thin-film transistor includes: a pair of n-type heavily doped regions that are horizontally spaced apart from each other; p-type channel regions that are located between the n-type heavily doped regions so as to face their associated gate electrodes, respectively;... | 12/07/2004 |
| 6825529 | Stress inducing spacers A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein th... | 11/30/2004 |
| 6825506 | Field effect transistor and method of fabrication The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then f... | 11/30/2004 |
| 6822297 | Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed ... | 11/23/2004 |
| 6818488 | Process for making a gate for a short channel CMOS transistor structure The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, ... | 11/16/2004 |
| 6815797 | Silicide bridged anti-fuse A silicide bridged anti-fuse and a method of forming the anti-fuse are disclosed. The silicide bridged anti-fuse can be formed with a tungsten plug metalization process that does not require any additional process steps. As a result, anti-fuses can be added to an el... | 11/09/2004 |
| 6815770 | MOS transistor having reduced source/drain extension sheet resistance The present invention provides a novel MOS transistor structure. The MOS transistor includes a gate electrode formed on a semiconductor substrate, and a gate oxide layer formed between the gate electrode and the semiconductor substrate. A spacer is formed on each si... | 11/09/2004 |
| 6815765 | Semiconductor device with function of modulating gain coefficient and semiconductor integrated circuit including the same A semiconductor device has a structure in which an impurity diffusion region with an impurity concentration lower than an impurity concentration of a source and a drain is formed between the source and drain and a channel below the gate, having an asymmetric shape w... | 11/09/2004 |
| 6809343 | Electro luminescence display device There is provided an electronic device having high reliability and high color reproducibility. A pixel structure is made such that a switching FET (201) and an electric current controlling FET (202) are formed on a single crystal semiconductor substrat... | 10/26/2004 |
| 6800891 | Self-aligned source pocket for flash memory cells An improved method for forming a flash memory is disclosed. A self-aligned source implanted pocket located underneath and around the source line junction is formed after the field oxide between adjacent word lines is removed, and before or after the self-aligned sou... | 10/05/2004 |
| 6794714 | Transistor and method for fabricating the same A transistor and a method for fabricating the same that involves a forming a device isolation oxide film semiconductor substrate, forming an opening in the device isolation oxide to open the substrate and define an active region, the junction between the oxide and t... | 09/21/2004 |
| 6787849 | Semiconductor devices and methods of manufacturing the same Embodiments include a semiconductor device including a well structure such that well areas can be formed with a higher density of integration and a plurality of high-voltage endurable transistors can be driven independently of one another with different voltages, an... | 09/07/2004 |
| 6784490 | High-voltage MOS transistor A high-voltage MOS transistor wherein a dopant concentration of a source offset region is set lower than a dopant concentration of a drain offset region whereby a resistance value of the resource region is set independently of a resistance value of the drain region ... | 08/31/2004 |
| 6784488 | Trench-gate semiconductor devices and the manufacture thereof A metal-oxide-semiconductor trench-gate semiconductor device in which a substantially intrinsic region (40) is provided below the gate trench (20), which extends from the base of the trench, substantially across the drain drift region (14) towar... | 08/31/2004 |
| 6777763 | Semiconductor device and method for fabricating the same In a thin film transistor (TFT), a mask is formed on a gate electrode, and a porous anodic oxide is formed in both sides of the gate electrode using a relatively low voltage. A barrier anodic oxide is formed between the gate electrode and the porous anodic oxide and... | 08/17/2004 |
| 6777711 | Semiconductor display device An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudina... | 08/17/2004 |
| 6774418 | Low dielectric silicon oxynitride spacer films and devices incorporating such films A method of depositing a silicon oxynitride spacer film on a gate stack in a semiconductor device involves contacting the gate stack with bistertiarybutylaminosilane (BTBAS), at least one nitrogen containing compound and oxygen (O2). The deposition is con... | 08/10/2004 |
| 6770921 | Sidewall strap for complementary semiconductor structures and method of making same Devices, structures, and methods for enhancing devices using dual-doped polycrystalline silicon are discussed. One aspect of the present invention includes a p-type strip having a top, a bottom, two sides, and two ends; an n-type strip having a top, a bottom, two si... | 08/03/2004 |
| 6762458 | High voltage transistor and method for fabricating the same In a high voltage transistor and a method for fabricating the same, a semiconductor substrate includes first, second, and third regions, the second and third regions neighboring the first region with boundaries. The first and second drift regions are respectively fo... | 07/13/2004 |
