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| Number | Title | Issue Date |
| 8159028 | Metal high dielectric constant transistor with reverse-T gate A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric ... | 04/17/2012 |
| 8159027 | Semiconductor device A semiconductor device including: a SiC substrate; an AlGaN layer formed on the SiC substrate; a source electrode and a drain electrode formed on the AlGaN layer so as to be spaced from each other; an insulation film formed between the source electrode and the drain... | 04/17/2012 |
| 8120107 | Semiconductor device internally having insulated gate bipolar transistor The semiconductor device includes a P-type semiconductor region and an MOS transistor. MOS transistor includes a gate electrode, a collector electrode, a drain electrode, an N-type impurity region and a P-type impurity region. N-type impurity region is electrically ... | 02/21/2012 |
| 8013391 | Power semiconductor devices with trenched shielded split gate transistor and methods of manufacture A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, active trenches extending through the well region and into t... | 09/06/2011 |
| 8008719 | Transistor structure having dual shield layers A semiconductor device is formed having lower gate to drain capacitance. A trench (80) is formed adjacent to a drain (20) of the semiconductor device. Trench (80) has a sidewall surface (100) and a surface (90). A doped region (... | 08/30/2011 |
| 7898029 | Semiconductor device internally having insulated gate bipolar transistor The semiconductor device includes a P-type semiconductor region and an MOS transistor. MOS transistor includes a gate electrode, a collector electrode, a drain electrode, an N-type impurity region and a P-type impurity region. N-type impurity region is electrically ... | 03/01/2011 |
| 7642596 | Insulated gate field effect transistor An insulated gate field effect transistor has a drain region (2,4), a body region (6) of opposite conductivity type and a source region (8) and an insulated gate (14) extending laterally over the body region (6), defining a channel... | 01/05/2010 |
| 7554154 | Bottom source LDMOSFET structure and method This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain ... | 06/30/2009 |
| 7528443 | Semiconductor device with recessed gate and shield electrode A semiconductor device includes a substrate having a recess, a gate electrode in the recess in the substrate, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. An insulating film is on at least on a surface of the gate el... | 05/05/2009 |
| 7521759 | Semiconductor device, method for manufacturing the same, and gate electrode structure A semiconductor structure includes (a) a semiconductor substrate having a channel region and a first integrated impurity diffusion region including a first electric field reduction region that is formed adjacent to the channel region and which includes a plurality o... | 04/21/2009 |
| 7495286 | High-voltage semiconductor device structure A high-voltage semiconductor device structure is provided, which includes a drain structure having two curved structures that are insulatedly adjacent to each other and alternatively arranged, and a source structure, a drain extension structure, and a gate structure... | 02/24/2009 |
| 7459751 | Insulated gate semiconductor device with small feedback capacitance and manufacturing method thereof Disclosed is an insulated gate semiconductor device including a first region having a gate electrode region and a first insulating film region surrounding the gate electrode region; a semiconductor region which includes a channel forming region and is disposed to op... | 12/02/2008 |
| 7432189 | Device with self aligned gaps for capacitance reduction A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler mate... | 10/07/2008 |
| 7427795 | Drain-extended MOS transistors and methods for making the same Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) ov... | 09/23/2008 |
| 7420247 | Power LDMOS transistor A LDMOS transistor comprises a trench formed through the epitaxial layer at least to the top surface of the substrate, the trench having a bottom surface and a sidewall contacting the source region and the portion of the channel region extending under the source reg... | 09/02/2008 |
| 7402875 | Lateral undercut of metal gate in SOI device Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate. ... | 07/22/2008 |
| 7382030 | Integrated metal shield for a field effect transistor The present invention relates to a semiconductor device having an integrated metal shield. The shield, created as part of a MOSFET, is formed about a gate electrode of the MOSFET to effectively reduce drain-to-gate capacitance and increase breakdown voltage. The shi... | 06/03/2008 |
| 7374982 | High voltage MOS transistor with gate extension A high voltage MOS transistor with a gate extension that has a reduced electric field in the drain region near the gate is provided. The high voltage MOS transistor includes a first and second gate layers, and a dielectric layer between the gate layers. The first an... | 05/20/2008 |
| 7372736 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell... | 05/13/2008 |
| 7371647 | Methods of forming transistors The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nit... | 05/13/2008 |
| 7372128 | Integrated circuit anti-interference outline structure The invention discloses an integrated circuit anti-interference outline structure for applications of integrated circuits capable of shielding the integrated circuit from invasions of external electromagnetic waves and leaks of internal electromagnetic waves, wherei... | 05/13/2008 |
| 7355262 | Diffusion topography engineering for high performance CMOS fabrication Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on t... | 04/08/2008 |
| 7355245 | Structure for reducing overlap capacitance in field effect transistors A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extend... | 04/08/2008 |
| 7345340 | Semiconductor integrated circuit and a semiconductor device A semiconductor integrated circuit that has a quick response to changes in source/drain electrode voltage having an LDMOS transistor. The transistor has a second conduction type first well region formed in a first conduction type semiconductor substrate; a first con... | 03/18/2008 |
| 7342266 | Field effect transistors with dielectric source drain halo regions and reduced miller capacitance A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor,... | 03/11/2008 |
| 7323422 | Dielectric layers and methods of forming the same High dielectric constant (high-k) materials are formed directly over oxidation-susceptible conductors such as silicon. A discontinuous layer is formed, with gaps between grains of the high-k material. Exposed conductor underneath the grain boundaries is oxidized or ... | 01/29/2008 |
| 7307314 | LDMOS transistor with improved gate shield A LDMOS transistor having a gate shield provides reduced drain coupling to the gate shield and source by restricting the thickness of the gate shield and by confining a source contact to the source region without overlap of the gate. ... | 12/11/2007 |
| 7304356 | IGBT or like semiconductor device of high voltage-withstanding capability A multiple-cell insulated-gate-bipolar-transistor chip is disclosed which includes a semiconductor substrate having formed therein a p+-type collector region and an n−-type base region, with a pn junction therebetween. An annular trench is et... | 12/04/2007 |
| 7304335 | Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performance and high scaling down density A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel... | 12/04/2007 |
| 7294885 | Reverse blocking semiconductor component with charge compensation The invention relates to a field effect controllable semiconductor component, comprising a semiconductor body with a first terminal zone and a second terminal zone, a channel zone formed between the two terminal zones, a control electrode, and also a plurality of co... | 11/13/2007 |
| 7283401 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell... | 10/16/2007 |
| 7276764 | Semiconductor device with metal wire layer masking An object of the present invention is to provide a semiconductor device capable of radiating electron-beams only to a desired region without forming a layer for restricting the radiating rays. A source electrode 22 made of aluminum prevents the generation of ... | 10/02/2007 |
| 7268046 | Dual gate oxide high-voltage semiconductor device and method for forming the same A dual gate oxide high-voltage semiconductor device and method for forming the same are provided. Specifically, a device formed according to the present invention includes a semiconductor substrate, a buried oxide layer formed over the substrate, a silicon layer for... | 09/11/2007 |
| 7265415 | MOS-gated transistor with reduced miller capacitance In one embodiment of the present invention, a trench MOS-gated transistor includes a first region of a first conductivity type forming a pn junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending d... | 09/04/2007 |
| 7253486 | Field plate transistor with reduced field plate resistance In one example embodiment, a transistor (100) is provided. The transistor (100) comprises a source (10), a gate (30), a drain (20), and a field plate (40) located between the gate (30) and the drain (20). The f... | 08/07/2007 |
| 7253482 | Structure for reducing overlap capacitance in field effect transistors A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extend... | 08/07/2007 |
| 7250343 | Power transistor arrangement and method for fabricating it In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor ar... | 07/31/2007 |
| 7235849 | Semiconductor device and method for fabricating the same The semiconductor device comprises a silicon substrate 10 having a device region 11, a transistor including a gate electrode 20 formed in the device region 11 with the gate insulation film 14 formed therebetween, and a dummy metal ... | 06/26/2007 |
| 7233043 | Triple-diffused trench MOSFET A trench-gated MOSFET includes adjacent mesas formed on opposite sides of a trench. A body region in the first mesa extends downward below the level of the trenches and laterally across the bottom of the trenches. The body region in the second mesa extends part of t... | 06/19/2007 |
| 7220651 | Transistor and method for manufacturing the same A transistor and a method for manufacturing the same are disclosed. One cell transistor having silicon-insulator-silicon (“SIS”) structure and two cell transistors having silicon-oxide-nitride-oxide-silicon (“SONOS”) structure constitute the transistor of th... | 05/22/2007 |
