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| Number | Title | Issue Date |
| 8110873 | High voltage transistor A high voltage transistor that includes a substrate where an active region is defined, a first impurity region and a second impurity region in the active region and a third impurity region between the first and second impurity regions, and a first gate electrode on ... | 02/07/2012 |
| 7898028 | Process for fabricating a strained channel MOSFET device A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlyin... | 03/01/2011 |
| 7847349 | Single-cycle FFT butterfly calculator In accordance with exemplary embodiments, a Fast Fourier Transform (FFT) architecture includes elements that perform a radix-2 FFT butterfly in one processor clock cycle at steady state. Some exemplary implementations of the FFT architecture incorporate register and... | 12/07/2010 |
| 7737495 | Semiconductor device having inter-layers with stress levels corresponding to the transistor type The present invention provides a semiconductor device including an N channel MIS type transistor and a P channel MIS type transistor. The semiconductor device includes a first inter-layer film formed on the NMIS transistor and having a tensile stress, and a second i... | 06/15/2010 |
| 7638840 | Semiconductor storage device and semiconductor integrated circuit A semiconductor storage device according to the present invention, comprising: a first semiconductor layer formed on a substrate via a buried insulation layer; an FBC (Floating Body Cell) having a channel body of floating type formed on the first semiconductor layer... | 12/29/2009 |
| 7511338 | Semiconductor device and manufacturing method of the same An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and th... | 03/31/2009 |
| 7453120 | Semiconductor structure A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in... | 11/18/2008 |
| 7436029 | High performance CMOS device structures and method of manufacture A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width... | 10/14/2008 |
| 7429770 | Semiconductor device and manufacturing method thereof A technique capable of reducing threshold voltage and reducing high-temperature heat treatment after forming a gate electrode is provided. An n-type MIS transistor or a p-type MIS transistor is formed on an active region isolated by an element isolation region of a ... | 09/30/2008 |
| 7427795 | Drain-extended MOS transistors and methods for making the same Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) ov... | 09/23/2008 |
| 7423324 | Double-gate MOS transistor, double-gate CMOS transistor, and method for manufacturing the same In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-sh... | 09/09/2008 |
| 7402864 | Method for forming a DRAM semiconductor device with a sense amplifier A method for forming a sense amplifier of a semiconductor device prevents bit lines from being bridged to each other by a stepped portion created on an insulation interlayer due to irregular density of a P-type impurity, which is ion-implanted into an insulation int... | 07/22/2008 |
| 7394156 | Semiconductor integrated circuit device and method of producing the same A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cel... | 07/01/2008 |
| 7388238 | Semiconductor integrated circuit device with reduced leakage current The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage cur... | 06/17/2008 |
| 7378709 | Oscillator with a guard ring formed around an N well and constituent components integrally formed on the N well, on a semiconductor substrate An oscillator capable of reducing a noise component when partly formed by using the CMOS process or the MOS process. A high-frequency amplifier circuit, a mixing circuit, a local oscillator 13, intermediate-frequency filters, an intermediate-frequency amplifi... | 05/27/2008 |
| 7365392 | Semiconductor device with integrated trench lateral power MOSFETs and planar devices Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same... | 04/29/2008 |
| 7361958 | Nonplanar transistors with metal gate electrodes A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first... | 04/22/2008 |
| 7345340 | Semiconductor integrated circuit and a semiconductor device A semiconductor integrated circuit that has a quick response to changes in source/drain electrode voltage having an LDMOS transistor. The transistor has a second conduction type first well region formed in a first conduction type semiconductor substrate; a first con... | 03/18/2008 |
| 7341896 | Method of manufacturing a vertical MOS transistor In a method of manufacturing a vertical MOS transistor, a body region, a trench, a gate oxide film, a gate electrode, a source region, and a body contact region are successively formed in a semiconductor substrate. A first insulating film is deposited over the main ... | 03/11/2008 |
| 7335948 | Integrated circuit incorporating higher voltage devices and low voltage devices therein An integrated circuit formed on a semiconductor substrate and configured to accommodate higher voltage devices and low voltage devices therein. In one embodiment, the integrated circuit includes a switch formed on the semiconductor substrate and a driver switch of a... | 02/26/2008 |
| 7332774 | Multiple-gate MOS transistor and a method of manufacturing the same Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is... | 02/19/2008 |
| 7326995 | Trench MIS device having implanted drain-drift region and thick bottom oxide A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. T... | 02/05/2008 |
| 7323751 | Thin film resistor integration in a dual damascene structure A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over t... | 01/29/2008 |
| 7315063 | CMOS transistor and method of manufacturing the same A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. T... | 01/01/2008 |
| 7312125 | Fully depleted strained semiconductor on insulator transistor and method of making the same An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and... | 12/25/2007 |
| 7304348 | DMOS transistor A lateral CMOS-compatible RF-DMOS transistor (RFLDMOST) with low ‘on’ resistance, characterised in that disposed in the region of the drift space (20) which is between the highly doped drain region (5) and the control gate (9) and above the ... | 12/04/2007 |
| 7291884 | Trench MIS device having implanted drain-drift region and thick bottom oxide A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the t... | 11/06/2007 |
| 7291528 | Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germ... | 11/06/2007 |
| 7288822 | Semiconductor structure and fabricating method thereof A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second co... | 10/30/2007 |
| 7279746 | High performance CMOS device structures and method of manufacture A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width... | 10/09/2007 |
| 7279399 | Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/09/2007 |
| 7271455 | Formation of fully silicided metal gate using dual self-aligned silicide process An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of for... | 09/18/2007 |
| 7271442 | Transistor structure having stressed regions of opposite types underlying channel and source/drain regions An integrated circuit and method of fabrication are provided in which the integrated circuit includes a field effect transistor (FET) having a channel region and source and drain regions adjacent to the channel region. A first stressed region having a first type of ... | 09/18/2007 |
| 7268395 | Deep trench super switch device A deep trench super switch device has a plurality of trenches, each of the trenches containing a gate electrode polysilicon layer on top of a plurality of stacked conductive floating polysilicon layers, the remainder of each of the trenches being filled with a nonco... | 09/11/2007 |
| 7265434 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 09/04/2007 |
| 7265388 | Semiconductor device A semiconductor device formed on a silicon carbide semiconductor substrate comprises an epitaxial layer formed on a surface sloping (or inclining) by 0 to less than 1 degree from a (000-1) face of the silicon carbide semiconductor substrate, wherein at least one of ... | 09/04/2007 |
| 7253472 | Method of fabricating semiconductor device employing selectivity poly deposition A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gat... | 08/07/2007 |
| 7247534 | Silicon device on Si:C-OI and SGOI and method of manufacture A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second mat... | 07/24/2007 |
| 7244994 | Laterally diffused metal oxide semiconductor device and method of forming the same A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide ... | 07/17/2007 |
| 7242059 | Semiconductor device having DMOS and CMOS on single substrate A semiconductor device includes a P-type semiconductor substrate, a P-channel DMOS transistor, a CMOS transistor. The P-channel DMOS transistor is disposed on the P-type semiconductor substrate and includes a drain formed of the P-type semiconductor substrate and a ... | 07/10/2007 |
