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| Number | Title | Issue Date |
| 8183630 | Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT A microelectronic device including: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transis... | 05/22/2012 |
| 8134204 | DEMOS transistors with STI and compensated well in drain A drain extended MOS (DEMOS) transistor with an element of field oxide separating the drain contact from the gate, and a compensation region of opposite polarity in the drain under the gate, is disclosed. The inventive DEMOS may be fabricated in a CMOS IC without ad... | 03/13/2012 |
| 7960785 | Semiconductor integrated circuit devices A semiconductor integrated circuit device may include: a substrate that includes a high-voltage device region and a low-voltage device region defined on the substrate; a first buried impurity layer formed in at least a portion of the high-voltage device region and c... | 06/14/2011 |
| 7898027 | Metal-oxide-semiconductor device A MOS device includes a semiconductor substrate having a first conductive type, a source region, a gate structure, and a drain region having a second conductive type. The gate structure is formed on the semiconductor substrate and substantially parallel to a first d... | 03/01/2011 |
| 7868383 | Configurable non-volatile logic structure for characterizing an integrated circuit device An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes ... | 01/11/2011 |
| 7851856 | True CSP power MOSFET based on bottom-source LDMOS A semiconductor package may comprise a semiconductor substrate, a MOSFET device having a plurality cells formed on the substrate, and a source region common to all cells disposed on a bottom of the substrate. Each cell comprises a drain region on a top of the semico... | 12/14/2010 |
| 7847348 | Semiconductor apparatus Provided is a semiconductor apparatus including a substrate region, an active region on the substrate region, a gate pattern on the active region, and first and second impurities-doped regions along both edges of the active region that do not overlap the gate patter... | 12/07/2010 |
| 7812394 | CMOS transistor junction regions formed by a CVD etching and deposition sequence This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent dep... | 10/12/2010 |
| 7791138 | Semiconductor component and method A semiconductor component and method of making a semiconductor component. One embodiment provides a first metallization structure electrically coupled to charge compensation zones via an ohmic contact and to drift zones via a Schottky contact. A second metallization... | 09/07/2010 |
| 7436070 | Semiconductor device A non-insulated DC-DC converter hs a power MOS•FRT for a highside switch and a power MOS•FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS•FET for the highside switch and the power MOS•FET for the lowside switch, driver circuits t... | 10/14/2008 |
| 7427795 | Drain-extended MOS transistors and methods for making the same Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) ov... | 09/23/2008 |
| 7400016 | Semiconductor device realizing characteristics like a SOI MOSFET In a semiconductor device, source/drain layers have a low resistivity region and an extension region extending from the low resistivity region toward the channel region. The extension regions are lower in impurity concentration and shallower in depth than the low re... | 07/15/2008 |
| 7391080 | LDMOS transistor device employing spacer structure gates An integrated LDMOS transistor comprises a semiconductor substrate (11), an LDMOS gate region (17), LDMOS source (14) and drain (15) regions, and a channel region (13) arranged beneath the LDMOS gate region, where the channel regio... | 06/24/2008 |
| 7368784 | Thermal protection device for an integrated power MOS A thermal protection device is for an integrated power MOSFET transistor including an interdigitated array of source regions and drain regions defined in a well region of the monocrystalline silicon substrate, and gate structures overhanging channel regions defined ... | 05/06/2008 |
| 7358968 | Sustain driver, sustain control system, and plasma display The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating pow... | 04/15/2008 |
| 7355250 | Electrostatic discharge device with controllable holding current An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept be... | 04/08/2008 |
| 7355246 | Memory cell without halo implant Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with cha... | 04/08/2008 |
| 7348971 | Active matrix panel In an active matrix panel, a pixel matrix which includes a plurality of gate lines, a plurality of source lines, and thin film transistors is formed on a first transparent substrate. A second transparent substrate is formed opposite to the first transparent substrat... | 03/25/2008 |
| 7348599 | Semiconductor device and manufacturing method thereof A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at l... | 03/25/2008 |
| 7348630 | Semiconductor device for high frequency uses and manufacturing method of the same The semiconductor device has a semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a pair of impurity diffusion layers formed in a surface layer of the semiconductor substrate at both sides of each of the gate electrodes. The semic... | 03/25/2008 |
| 7345340 | Semiconductor integrated circuit and a semiconductor device A semiconductor integrated circuit that has a quick response to changes in source/drain electrode voltage having an LDMOS transistor. The transistor has a second conduction type first well region formed in a first conduction type semiconductor substrate; a first con... | 03/18/2008 |
| 7335593 | Method of fabricating semiconductor device A gate metal is formed in a film, the foregoing gate metal is partially etched per each TFT having a different property, and a gate electrode is fabricated. Specifically, a resist mask is fabricated by exposing a resist to light per each TFT having a different prope... | 02/26/2008 |
| 7309909 | Leadframes for improved moisture reliability of semiconductor devices A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (402) and a plurality of lead segments (403). Covering the base metal are, consecutively, a nickel layer (3... | 12/18/2007 |
| 7301202 | Semiconductor device and method of manufacturing the same A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semicon... | 11/27/2007 |
| 7285822 | Power MOS device A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a ... | 10/23/2007 |
| 7279194 | Thin film formation apparatus and method of manufacturing self-light-emitting device using thin film formation apparatus A means of effectively applying an organic EL material application liquid with good application liquid cut-off is provided. A heater and an ultrasonic oscillator are formed in a thin film formation apparatus when applying the application liquid, and heat and ultraso... | 10/09/2007 |
| 7250655 | MOS transistor having a T-shaped gate electrode A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to... | 07/31/2007 |
| 7235810 | Semiconductor device and method of fabricating the same There is provided a crystalline TFT in which reliability comparable to or superior to a MOS transistor can be obtained and excellent characteristics can be obtained in both an on state and an off state. A gate electrode of the crystalline TFT is formed of a laminate... | 06/26/2007 |
| 7230299 | Power switch structure with low RDSon and low current limit and method In one embodiment, a power switch device (33) includes a first MOSFET device 41 and a second MOSFET device (42). A split gate structure (84) including a first gate electrode (48,87) controls the first MOSFET device (41). A s... | 06/12/2007 |
| 7221021 | Method of forming high voltage devices with retrograde well A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the... | 05/22/2007 |
| 7217977 | Covert transformation of transistor properties as a circuit protection method A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are ap... | 05/15/2007 |
| 7208762 | Semiconductor device and manufacturing method thereof A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at l... | 04/24/2007 |
| 7202529 | Field effect transistor A field effect transistor includes a substrate having a doping of a first conductivity type, a drain area in the substrate having a doping of a second conductivity type oppposite the first conductivity type, a source area in the substrate being laterally spaced from... | 04/10/2007 |
| 7202549 | Semiconductor device having thin film resistor protected from oxidation A semiconductor device, a method for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes a substrate section, a resistor formed on the substrate section, a metal patter... | 04/10/2007 |
| 7176523 | Power mosfet having conductor plug structured contacts In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-t... | 02/13/2007 |
| 7176553 | Integrated resistive elements with silicidation protection In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a pre-determined resistivity... | 02/13/2007 |
| 7173308 | Lateral short-channel DMOS, method for manufacturing same and semiconductor device A lateral short-channel DMOS includes an epitaxial layer formed on a semiconductor substrate. A first conductivity-type well is formed in the epitaxial layer. A second conductivity-type well is formed in the first conductivity-type well and includes a channel formin... | 02/06/2007 |
| 7166515 | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering A camouflaged interconnection for interconnecting two spaced-apart regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first region forming a conducting channel between th... | 01/23/2007 |
| 7144785 | Method of forming isolation trench with spacer formation A strained silicon semiconductor arrangement with a shallow trench isolation (STI) structure has a strained silicon (Si) layer formed on a silicon germanium (SiGe) layer. A trench extends through the Si layer into the SiGe layer, and sidewall spacers are employed th... | 12/05/2006 |
| 7126156 | Thin film transistor display device with integral control circuitry A semiconductor device includes a control circuit for carrying out gamma correction of a supplied signal, and a memory for storing data used in the gamma correction. The control circuit and the memory are constituted by TFTs, and are integrally formed on the same in... | 10/24/2006 |
