Bizarre Patents
A sealed crustless sandwich for providing a convenient sandwich without an outer crust which can be stored for long periods of time without a central filling from leaking outwardly.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8183625 | NROM flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the ga... | 05/22/2012 |
| 8183624 | Semiconductor memory device A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second uppe... | 05/22/2012 |
| 8169018 | Non-volatile memory device A non-volatile memory device includes a semiconductor layer including a cell region and a peripheral region, a cell region gate structure disposed in the cell region of the semiconductor layer, and wherein the cell region gate structure includes a tunneling insulati... | 05/01/2012 |
| 8159020 | Non-volatile two transistor semiconductor memory cell and method for producing the same The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2 ) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory... | 04/17/2012 |
| 8143667 | Semiconductor device having non-volatile memory and method of fabricating the same A memory cell of a non-volatile memory device, comprises: a select transistor gate of a select transistor on a substrate, the select transistor gate comprising: a gate dielectric pattern; and a select gate on the gate dielectric pattern; first and second memory cell... | 03/27/2012 |
| 8134203 | Nonvolatile semiconductor memory device In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insul... | 03/13/2012 |
| 8129776 | Semiconductor device A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array ar... | 03/06/2012 |
| 8110867 | Semiconductor device and method of manufacturing the same A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region ... | 02/07/2012 |
| 8106445 | Nonvolatile semiconductor memory device and method of manufacturing the same A nonvolatile semiconductor memory device comprises a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top... | 01/31/2012 |
| 8093650 | Scalable electrically eraseable and programmable memory (EEPROM) cell array A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of t... | 01/10/2012 |
| 8080844 | Semiconductor device A semiconductor device suppresses short-circuit failure between a selection gate electrode and a control gate electrode while shortening the distance between the upper portions of the selection gate electrode and the control gate electrode. The device includes an im... | 12/20/2011 |
| 8072025 | Non-volatile semiconductor storage device and method of manufacturing the same A first lamination part includes: a charge accumulation layer provided on the respective sidewalls of laminated first conductive layers and accumulating charges; and a first semiconductor layer provided in contact with the fourth insulation layer and formed to exten... | 12/06/2011 |
| 8053829 | Methods of fabricating nonvolatile memory devices Nonvolatile memory devices and methods of manufacturing nonvolatile memory devices are provided. The method includes patterning a bulk substrate to form an active pillar; forming a charge storage layer on a side surface of active pillar; and forming a plurality of g... | 11/08/2011 |
| 8053828 | Nonvolatile semiconductor memory device and manufacturing method thereof First and second memory cells have first and second channels, first and second tunnel insulating films, first and second charge storage layers formed of an insulating film, first and second block insulating films, and first and second gate electrodes. A first select... | 11/08/2011 |
| 8044456 | Nonvolatile semiconductor memory device and producing method thereof A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeat... | 10/25/2011 |
| 8039891 | Split charge storage node outer spacer process Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techn... | 10/18/2011 |
| 8030701 | Memory cell of nonvolatile semiconductor memory device A memory cell of a nonvolatile semiconductor memory device according to an embodiment of the invention has a MONOS structure. The charge storage layer of the memory cell includes insulating material layers. The relationship between the conduction band edge energy an... | 10/04/2011 |
| 8026546 | Nonvolatile semiconductor memory device and method of manufacturing the same A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alt... | 09/27/2011 |
| 8022469 | Semiconductor device and manufacturing method thereof The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterize... | 09/20/2011 |
| 8008710 | Non-volatile semiconductor storage device A memory string has a semiconductor layer with a joining portion that is formed to join a plurality of columnar portions extending in a vertical direction with respect to a substrate and lower ends of the plurality of columnar portions. First conductive layers are f... | 08/30/2011 |
| 7973357 | Non-volatile memory devices Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrat... | 07/05/2011 |
| 7968935 | Reconfigurable semiconductor device A reconfigurable semiconductor device is disclosed. The semiconductor device includes a substrate, a first insulating material formed on the substrate, two channels having different polarities, a plurality of terminal electrodes formed on the insulating material and... | 06/28/2011 |
| 7964909 | Scalable high density non-volatile memory cells in a contactless memory array A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and a trench diffusion area is formed under each trench. A vertical, non... | 06/21/2011 |
| 7956408 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device relating to one embodiment of this invention includes a substrate, a plurality of memory strings formed on said substrate, said memory string having a first select gate transistor, a plurality of memory cells and a second se... | 06/07/2011 |
| 7952136 | Nonvolatile semiconductor storage apparatus and method for manufacturing the same According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a substrate; a columnar semiconductor disposed perpendicular to the substrate; a charge storage laminated film disposed around the columnar se... | 05/31/2011 |
| 7948026 | Non-volatile semiconductor memory device and method of manufacturing the same A method of manufacturing a non-volatile semiconductor memory device including previously forming a recess in a first peripheral region on a semiconductor substrate, forming a first gate insulator having a first thickness in the recess, forming a second gate insulat... | 05/24/2011 |
| 7928504 | Semiconductor memory device and method for manufacturing the same A semiconductor memory device and a method for manufacturing the same are disclosed, which reduce parasitic capacitance generated between a storage node contact and a bit line of a high-integration semiconductor device. A method for manufacturing a semiconductor mem... | 04/19/2011 |
| 7915669 | NROM flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the ga... | 03/29/2011 |
| 7910981 | Semiconductor device and method of manufacturing the same A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a... | 03/22/2011 |
| 7902593 | Memory device and method of manufacturing the same In a memory device and a method of manufacturing the memory device, a source contact connected to a common source line may be formed on a drain region instead of a source region. A transistor having a negative threshold voltage may be formed between the source regio... | 03/08/2011 |
| 7880221 | Forming metal-semiconductor films having different thicknesses within different regions of an electronic device A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implante... | 02/01/2011 |
| 7872299 | Nonvolatile memory devices and methods of fabricating the same Provided are nonvolatile memory devices and methods of fabricating the same which may prevent or reduce deterioration of device characteristics and deterioration of a breakdown voltage. The nonvolatile memory device may include a semiconductor substrate, a charge-tr... | 01/18/2011 |
| 7868377 | Layout and structure of memory A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the spa... | 01/11/2011 |
| 7851851 | Three dimensional NAND memory A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined b... | 12/14/2010 |
| 7842997 | Nonvolatile memory device having cell and peripheral regions and method of making the same A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive... | 11/30/2010 |
| 7842998 | Nonvolatile semiconductor memory device and method for manufacturing the same According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a semiconductor substrate; memory cell transistors that are series-connected; and a select transistor that includes: a first diffusion region that... | 11/30/2010 |
| 7808036 | Memory device and method of fabricating the same A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of e... | 10/05/2010 |
| 7804128 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device according to an example of the present invention includes a semiconductor region, source/drain areas arranged separately in the semiconductor region, a tunnel insulating film arranged on a channel region between the source/d... | 09/28/2010 |
| 7781825 | Semiconductor device and method for manufacturing the same A semiconductor device includes an insulating layer, a channel structure, an insulating structure and a gate. The channel structure includes a channel bridge for connecting two platforms. The bottom of the channel bridge is separated from the insulating layer by a d... | 08/24/2010 |
| 7741674 | Non-volatile memory with source/drains in multiple directions An object is to improve a data recording amount per memory cell. In the invention, in a non-volatile memory, the data contents of which can be electrically written and erased, each memory cell that configures the non-volatile memory is provided with: source/drain re... | 06/22/2010 |
