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| Number | Title | Issue Date |
| 8125021 | Non-volatile memory devices including variable resistance material A non-volatile memory device includes a first oxide layer, a second oxide layer and a buffer layer formed on a lower electrode. An upper electrode is formed on the buffer layer. In one example, the lower electrode is composed of at least one of Pt, Ru, Ir, IrOx and ... | 02/28/2012 |
| 8053827 | Semiconductor device and method for manufacturing the same It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: formin... | 11/08/2011 |
| 8039890 | Random number generating device A random number generating device includes a semiconductor device including a source region, a drain region, a channel region provided between the source region and the drain region, and an insulating portion provided on the channel region, the insulating portion in... | 10/18/2011 |
| 8022468 | Ultraviolet radiation blocking interlayer dielectric A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a... | 09/20/2011 |
| 7999308 | Nonvolatile semiconductor memory element with silicon nitride charge trapping film having varying hydrogen concentration To improve a charge retention characteristic of a nonvolatile memory transistor. A first insulating film, a charge trapping film, and a second insulating film are formed between a semiconductor substrate and a conductive film. The charge trapping film is formed of a... | 08/16/2011 |
| 7964908 | Memory devices comprising nano region embedded dielectric layers In one aspect, a memory cell includes a plurality of dielectric layers located within a charge storage gate structure. At least one of the dielectric layers includes an dielectric material including oxygen, and nano regions including oxygen embedded in the dielectri... | 06/21/2011 |
| 7943984 | Nonvolatile semiconductor memory apparatus A nonvolatile semiconductor memory apparatus includes: a memory element including: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the s... | 05/17/2011 |
| 7915668 | Semiconductor device and method for forming the same A memory device includes an insulating layer formed over a substrate, a gate formed over the insulating layer, and charge storage elements disposed over the insulating layer. The charge storage elements are separated from each other and are electrically insulated, a... | 03/29/2011 |
| 7898022 | Scalable multi-functional and multi-level nano-crystal non-volatile memory device A multi-functional and multi-level memory cell is comprised of a tunnel layer formed over a substrate. In one embodiment, the tunnel layer is comprised of two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel lay... | 03/01/2011 |
| 7880220 | Non-volatile memory device and fabrication method of non-volatile memory device and memory apparatus including non-volatile memory device A non-volatile memory device is capable of reducing an excessive leakage current due to a rough surface of a polysilicon and realizing improved blocking function with an oxide film that is thinner by forming a first oxide film and a second oxide film including a sil... | 02/01/2011 |
| 7851850 | Band engineered nano-crystal non-volatile memory device utilizing enhanced gate injection Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal charge trapping in EEPROM and block erasable memory devices, such as Flash memory devices. Embodiments of ... | 12/14/2010 |
| 7829938 | High density NAND non-volatile memory device Non-volatile memory devices and arrays are described that utilize dual gate (or back-side gate) non-volatile memory cells with band engineered gate-stacks that are placed above or below the channel region in front-side or back-side charge trapping gate-stack configu... | 11/09/2010 |
| 7800164 | Nanocrystal non-volatile memory cell and method therefor A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to f... | 09/21/2010 |
| 7745874 | Floating gate having multiple charge storing layers, method of fabricating the floating gate, non-volatile memory device using the same, and fabricating method thereof Provided is a floating gate having multiple charge storing layers, a non-volatile memory device using the same, and a method of fabricating the floating gate and the non-volatile memory device, in which the multiple charge storing layers using metal nano-crystals of... | 06/29/2010 |
| 7737488 | Blocking dielectric engineered charge trapping memory cell with high speed erase A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated fro... | 06/15/2010 |
| 7728379 | Semiconductor device and method of manufacturing same A semiconductor device includes: a semiconductor layer; an insulating film provided on the semiconductor layer; and a charge storage layer provided on the insulating film. The semiconductor layer has a channel formation region in its surface portion. The insulating ... | 06/01/2010 |
| 7687850 | Semiconductor device This invention is to improve data retention properties of a nonvolatile memory cell having an ONO film. A first cavity is disposed, in a position between the nitride film serving as a charge storage film and a memory gate and below an end portion of the memory gate,... | 03/30/2010 |
| 7655971 | Nonvolatile semiconductor memory device and method for manufacturing the same A nonvolatile semiconductor memory device includes: a source region and a drain region formed at a distance from each other in a semiconductor substrate; a tunnel insulating film formed on the semiconductor substrate between the source region and the drain region; a... | 02/02/2010 |
| 7646056 | Gate structures of a non-volatile memory device and methods of manufacturing the same In a gate structure of a non-volatile memory device is formed, a tunnel insulating layer and a charge trapping layer are formed on a substrate. A composite dielectric layer is formed on the charge trapping layer and has a laminate structure in which first material l... | 01/12/2010 |
| 7521751 | Nonvolatile memory device To provide a nonvolatile memory device suppressing a reduction of a data retention characteristic even if charges injected and stored into a local area of a nitride film is redistributed to achieve a reduction of voltage, the nonvolatile memory device in which hot e... | 04/21/2009 |
| 7442989 | Nonvolatile semiconductor memory device and method of manufacturing thereof This invention is intended to improve reliability of a nonvolatile semiconductor memory device and reduces a memory cell size of the nonvolatile semiconductor memory device. A memory cell which includes source/drain diffusion layers in a p-type well formed in a sili... | 10/28/2008 |
| 7432548 | Silicon lanthanide oxynitride films Electronic apparatus and methods of forming the electronic apparatus include a silicon lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The silicon lanthanide oxynitride film may be arranged as a layered structure having one or m... | 10/07/2008 |
| 7423326 | Integrated circuits with composite gate dielectric CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface. ... | 09/09/2008 |
| 7405166 | Method of manufacturing charge storage device A method of manufacturing a charge storage device is provided. Utilizing the capacity for a precise control of the thickness and the silicon content of a deposited film in an atomic layer deposition process, a stacked gradual material layer such as a hafnium silicon... | 07/29/2008 |
| 7400012 | Scalable Flash/NV structures and devices with extended endurance Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an inject... | 07/15/2008 |
| 7391072 | Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which h... | 06/24/2008 |
| 7391078 | Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace... | 06/24/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| 7371647 | Methods of forming transistors The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nit... | 05/13/2008 |
| 7372096 | Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which h... | 05/13/2008 |
| 7372097 | Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which h... | 05/13/2008 |
| 7365389 | Memory cell having enhanced high-K dielectric A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory... | 04/29/2008 |
| 7352024 | Semiconductor storage device and semiconductor integrated circuit There is provided a semiconductor storage device capable of high integration. On a top surface of a semiconductor substrate, a plurality of device isolation regions (16) each extending and meandering in a lateral direction are formed so as to be arrayed with ... | 04/01/2008 |
| 7342280 | Non-volatile memory and method of fabricating the same An electrically erasable programmable read-only memory (EEPROM) comprises trench isolation regions whose upper surfaces are recessed compared with an upper surface of the semiconductor substrate, thereby allowing use of all surfaces of a protrusion of the semiconduc... | 03/11/2008 |
| 7335941 | Uniform channel programmable erasable flash EEPROM A new method to form a split gate for a flash device in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A film is deposited overlying the substrate. The film comprises a second dielectric layer overlying a fir... | 02/26/2008 |
| 7332768 | Non-volatile memory devices Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, program... | 02/19/2008 |
| 7294880 | Semiconductor non-volatile memory cell with a plurality of charge storage regions For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical... | 11/13/2007 |
| 7276762 | NROM flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the ga... | 10/02/2007 |
| 7265414 | NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of a nanolaminate structure. The NROM memory cell has a substrat... | 09/04/2007 |
| 7265413 | Semiconductor memory with vertical memory transistors and method for fabricating it The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned ste... | 09/04/2007 |
