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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 8154072 | Nonvolatile semiconductor memory apparatus A nonvolatile semiconductor memory apparatus includes: a source and drain regions formed at a distance from each other in a semiconductor layer; a first insulating film formed on the semiconductor layer located between the source region and the drain region, the fir... | 04/10/2012 |
| 8004034 | Single poly type EEPROM and method for manufacturing the EEPROM Embodiments relate to a single poly type EEPROM and a method for manufacturing an EEPROM. According to embodiments, a single poly type EEPROM may include unit cells. A unit cell may include a floating gate at a side of a control node formed on and/or over a semicond... | 08/23/2011 |
| 7847339 | Semiconductor integrated circuit devices having conductive patterns that are electrically connected to junction regions A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applyin... | 12/07/2010 |
| 7449747 | Semiconductor memory device Flash memory is rapidly decreasing in price. There is a demand for a new memory system that permits size reduction and suits multiple-value memory. A flash memory of AND type suitable for multiple-value memory with multiple-level threshold values can be made small i... | 11/11/2008 |
| 7439574 | Silicon/oxide/nitride/silicon nonvolatile memory with vertical channels Provided are a silicon/oxide/nitride/oxide/silicon (SONOS) memory, a fabricating method thereof, and a memory programming method. The SONOS memory includes a substrate; a first insulating layer stacked on the substrate; a semiconductor layer, which is patterned on t... | 10/21/2008 |
| 7436707 | Flash memory cell structure and operating method thereof A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and ... | 10/14/2008 |
| RE40486 | Self-aligned non-volatile memory cell Disclosed is a self-aligned non-volatile memory cell including a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both for... | 09/09/2008 |
| 7394127 | Non-volatile memory device having a charge storage oxide layer and operation thereof A non-volatile memory device includes a pair of source/drain regions disposed in a semiconductor substrate, having a channel region between them. A charge storage oxide layer is disposed on the channel region and overlaps part of each of the pair of source/drain reg... | 07/01/2008 |
| 7391078 | Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace... | 06/24/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| 7348625 | Semiconductor device and method of manufacturing the same An EEPROM cell includes first and second assist gates on opposite sides of a charge retaining insulating layer. Current in the EEPROM memory cell flows between inversion layers, which are created in response to a bias applied to the assist gates. The insulating laye... | 03/25/2008 |
| 7339230 | Structure and method for making high density mosfet circuits with different height contact lines Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits include a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate lay... | 03/04/2008 |
| 7335938 | Nonvolatile semiconductor memory and a fabrication method for the same A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectiv... | 02/26/2008 |
| 7312491 | Charge trapping semiconductor memory element with improved trapping dielectric A semiconductor memory element, which can be controlled via field effect, includes a semiconductor substrate of a first conduction type, a first doping region of a second conduction type provided in the semiconductor substrate, a second doping region of the second c... | 12/25/2007 |
| 7309893 | Semiconductor device and method of fabricating the same A semiconductor device includes a substrate having a pair of first diffused regions, and a gate including an oxide film provided on the substrate, and a charge storage layer provided on the oxide film, the charge storage layer being an electrical insulator capable o... | 12/18/2007 |
| 7301197 | Non-volatile nanocrystal memory transistors using low voltage impact ionization A low voltage non-volatile charge storage transistor has a nanocrystal layer for permanently storing charge until erased. A subsurface charge injector generates secondary carriers by stimulating electron-hole current flowing toward the substrate, with some carriers ... | 11/27/2007 |
| 7288809 | Flash memory with buried bit lines A memory cell and a method of forming the same are described. The memory cell is formed on a substrate. The memory cell includes a floating gate that is formed at least in part within the substrate. A bit line region is formed within the substrate in proximity to th... | 10/30/2007 |
| 7274068 | Ballistic direct injection NROM cell on strained silicon structures A nitride read only memory cell comprising a silicon-germanium layer with a pair of source/drain regions. A strained silicon layer is formed overlying the silicon-germanium layer such that the pair of source/drain regions is linked by a channel that is generated in ... | 09/25/2007 |
| 7268387 | Semiconductor device and an electronic device The present invention provides a semiconductor nonvolatile memory in which writing or erasing of storing information can be carried out at a high speed with low consumption power and in which dispersion width of a threshold voltage after writing or erasing is very n... | 09/11/2007 |
| 7265412 | Semiconductor memory device having memory cells requiring no refresh operation A memory cell includes first and second data holding portions for holding stored data and its inverted data. First and second p channel TFT compensate for charges leaked from first and second capacitors, respectively. A first (second) access transistor has first and... | 09/04/2007 |
| 7262457 | Non-volatile memory cell A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is form... | 08/28/2007 |
| 7262992 | Hearing aid A hearing aid comprising a data memory includes a plurality of semiconductor memory cells. The semiconductor memory cell has a gate insulating film formed on a semiconductor substrate, on a well region provided in the semiconductor substrate, or on a semiconductor f... | 08/28/2007 |
| 7259420 | Multiple-gate device with floating back gate Disclosed is a multiple-gate transistor that includes a channel region and source and drain regions at ends of the channel region. A gate oxide is positioned between a logic gate and the channel region and a first insulator is formed between a floating gate and the ... | 08/21/2007 |
| 7253468 | Flash memory and methods of fabricating the same Flash memory and methods of fabricating the same are disclosed. An illustrated example flash memory includes a first source formed within a semiconductor substrate; an epitaxial layer formed on an upper surface of the semiconductor substrate; an opening formed withi... | 08/07/2007 |
| 7250652 | Nonvolatile semiconductor memory device including an assistant gate formed in a trench A nonvolatile semiconductor memory device includes a substrate, a central structure, a second gate insulating film, a floating gate, and a control gate. The substrate has a trench. The central structure is formed so as to be embedded in the trench and protruded from... | 07/31/2007 |
| 7232729 | Method for manufacturing a double bitline implant The present invention provides a method of fabricating a doped semiconductor region comprising selectively implanting a first impurity to form a shallow heavily doped region. The method further comprises selectively implanting the first impurity to also form a deep ... | 06/19/2007 |
| 7221586 | Memory utilizing oxide nanolaminates Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region b... | 05/22/2007 |
| 7211482 | Method of forming a memory cell having self-aligned contact regions A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over ... | 05/01/2007 |
| 7212437 | Charge coupled EEPROM device and corresponding method of operation This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor substrate having a first conductivity; a plurality of gate structures for storing charge in a non-volatile manner... | 05/01/2007 |
| 7208794 | High-density NROM-FINFET Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence ... | 04/24/2007 |
| 7202770 | Voltage variable material for direct application and devices employing same The present invention provides overvoltage circuit protection. Specifically, the present invention provides a voltage variable material (“VVM”) that includes an insulative binder that is formulated to intrinsically adhere to conductive and nonconductive surfaces... | 04/10/2007 |
| 7202524 | Nonvolatile memory device and method of manufacturing the same A nonvolatile memory device is provided which includes a floating gate having a lower portion formed in a trench defined in a surface of a substrate and an upper portion protruding above the surface of the substrate from the lower portion. A gate insulating layer is... | 04/10/2007 |
| 7195967 | Nonvolatile semiconductor memory device and manufacturing method thereof In a channel region between the source/drain diffusion layers, impurities of the same conductivity type as the well are doped in an area apart from the diffusion regions. By using as a mask the gate formed in advance, tilted ion implantation in opposite directions i... | 03/27/2007 |
| 7187043 | Memory function body, particle forming method therefor and, memory device, semiconductor device, and electronic equipment having the memory function body A memory function body has a medium interposed between a first conductor (e.g., a conductive substrate) and a second conductor (e.g., an electrode) and consisting of a first material (e.g., silicon oxide or silicon nitride). The medium contains particles. Each parti... | 03/06/2007 |
| 7187587 | Programmable memory address and decode circuits with low tunnel barrier interpoly insulators Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the ou... | 03/06/2007 |
| 7183662 | Memory devices with memory cell transistors having gate sidewell spacers with different dielectric properties A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and secon... | 02/27/2007 |
| 7170129 | Non-volatile memory, fabrication method thereof and operation method thereof A method of fabrication a non-volatile memory is provided. A stacked structure is formed on a substrate, the stacked structure including a gate dielectric layer and a control gate. Then, a first dielectric layer, a second dielectric layer and a third dielectric laye... | 01/30/2007 |
| 7154141 | Source side programming A flash EEPROM array having a double-diffused source junction that can be used for source side programming. The flash EEPROM array, when programmed from the source side exhibits fast programming rates. Additionally, source side programming of arrays having different... | 12/26/2006 |
| 7151293 | SONOS memory with inversion bit-lines A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermo... | 12/19/2006 |
| 7145808 | Nonvolatile semiconductor memory apparatus and method of producing the same A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/dr... | 12/05/2006 |
