Bizarre Patents
Crispy Chip Sandwich and Process of Producing a Sandwich Product
A food product comprising a multilayer cookie or snack having outer layers formed from a crispy type edible food product such as a potato chip or corn chip, etc. with an intermediate marshmallow layer being in contact with the inner surface of each crispy chip and one or more filler substances.
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| Number | Title | Issue Date |
| 8154071 | Nonvolatile semiconductor memory device and method for fabricating nonvolatile semiconductor memory device According to an aspect of the present invention, there is provided a method for fabricating a nonvolatile semiconductor memory device including a memory cell being formed in a first region of a semiconductor substrate and a periphery circuit being formed in a second... | 04/10/2012 |
| 8115247 | Non-volatile semiconductor memory device having an erasing gate A non-volatile semiconductor memory device includes a floating gate formed above a semiconductor substrate; an erasing gate formed above the floating gate; a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position c... | 02/14/2012 |
| 8093648 | Method for manufacturing non-volatile memory and structure thereof A method for manufacturing a non-volatile memory and a structure thereof are provided. The manufacturing method comprises the following steps. Firstly, a substrate is provided. Next, a semiconductor layer is formed on the substrate. Then, a Si-rich dielectric layer ... | 01/10/2012 |
| 8076712 | Semiconductor memory comprising dual charge storage nodes and methods for its fabrication A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of sem... | 12/13/2011 |
| 8039889 | Non-volatile memory devices including stepped source regions and methods of fabricating the same A non-volatile memory device includes a semiconductor substrate having a first section including a substantially planar first top surface, a second section including a substantially planar second top surface, and a sidewall extending between the first and second top... | 10/18/2011 |
| 7989874 | Nonvolatile memory device and method for manufacturing the same The present invention discloses a nonvolatile memory device which can improve the data storage capacity without increasing the surface area of the device, and a method for manufacturing the same. The nonvolatile memory device comprises: a gate of a stack type struct... | 08/02/2011 |
| 7880217 | Programmable non-volatile memory (PNVM) device A programmable non-volatile memory (PNVM) device and method of forming the same compatible with CMOS logic device processes to improve a process flow, the PNVM device including a semiconductor substrate active area; a gate dielectric on the active area; a floating g... | 02/01/2011 |
| 7855410 | Semiconductor memory devices having a floating gate with a projecting portion and methods of forming semiconductor memory devices having a floating gate with a projecting portion According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A fir... | 12/21/2010 |
| 7842995 | Multi-bit non-volatile memory devices and methods of fabricating the same A multi-bit non-volatile memory device may include a semiconductor substrate including a body and at least one pair of fins protruding above the body. A first insulation layer may be formed on the body between the at least one pair of fins. A plurality of pairs of c... | 11/30/2010 |
| 7737486 | Non-volatile semiconductor storage device and method for manufacturing the same A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain re... | 06/15/2010 |
| 7642594 | Electronic device including gate lines, bit lines, or a combination thereof An electronic device can include memory cells that are connected to gate lines, bit lines, or a combination thereof. In one embodiment, at least two sets of memory cells can be oriented substantially along a first direction, (e.g., rows or columns). A first gate lin... | 01/05/2010 |
| 7629639 | Nanotube- and nanocrystal-based non-volatile memory An embodiment is a transistor for non-volatile memory that combines nanocrystal and nanotube paradigm shifts. In particular an embodiment is a transistor-based non-volatile memory element that utilizes a carbon nanotube channel region and nanocrystal charge storage ... | 12/08/2009 |
| 7622767 | Semiconductor device with T-shaped gate electrode and hollow region adjacent the gate electrode In a semiconductor device, a SiN first protective insulating film is formed on a semiconductor layer. A T-shaped gate electrode is formed on the semiconductor layer. A SiN second protective insulating film spreads in an umbrella shape from above the T-shaped gate el... | 11/24/2009 |
| 7612403 | Low power non-volatile memory and gate stack Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells in NOR or NAND memory architectures that allow for direct tunnel pro... | 11/03/2009 |
| 7586145 | EEPROM flash memory device with jagged edge floating gate An EEPROM flash memory device having a floating gate electrode enabling a reduced erase voltage and method for forming the same, the floating gate electrode including an outer edge portion including multiple charge transfer pointed tips. ... | 09/08/2009 |
| 7582930 | Non-volatile memory and method for manufacturing non-volatile memory A coupling oxide film is formed on a silicon substrate, a polysilicon film is further formed thereupon, and a low-temperature oxide film is deposited to a thickness of 10 nm, for example. Next, a silicon nitride film is formed on this low-temperature oxide film, and... | 09/01/2009 |
| 7582929 | Electronic device including discontinuous storage elements An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of disconti... | 09/01/2009 |
| 7528438 | Non-volatile memory including assist gate A non-volatile memory is provided. An assist gate structure is formed on a substrate such that the width at the bottom of the assist gate structure is greater than the width at the top of the assist gate structure. A floating gate is formed on one side of the assist... | 05/05/2009 |
| 7508026 | Non-volatile semiconductor memory device having a two-layer gate electrode transistor and method of manufacturing the device A non-volatile semiconductor memory device has a gate insulating film formed on a semiconductor substrate between isolation regions, a first gate electrode formed on the gate insulating film, an intergate insulating film formed on the first gate electrode, and a sec... | 03/24/2009 |
| 7489006 | Nonvolatile semiconductor storage device and manufacturing method therefor A nonvolatile semiconductor storage device includes a semiconductor substrate; a plurality of isolation regions formed in the semiconductor substrate; an element-forming region formed between adjacent isolation regions; a first gate insulating film provided on the e... | 02/10/2009 |
| 7443725 | Floating gate isolation and method of making the same The present invention relates to a method for forming a set of floating gates which are isolated from each other by means of slits, as well as semiconductor devices using the floating gate. The present invention provides a method for manufacturing an array of semico... | 10/28/2008 |
| 7442988 | Semiconductor devices and methods of fabricating the same Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a seco... | 10/28/2008 |
| 7439572 | Stacked gate memory cell with erase to gate, array, and method of manufacturing A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injecton from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the fl... | 10/21/2008 |
| 7429766 | Split gate type nonvolatile memory device In a split gate type nonvolatile memory device, a supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore po... | 09/30/2008 |
| RE40486 | Self-aligned non-volatile memory cell Disclosed is a self-aligned non-volatile memory cell including a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both for... | 09/09/2008 |
| 7420253 | Three-gate transistor structure A transistor structure comprises a semiconductor element extending between a source zone and a drain zone, as well as three portions of gates disposed on different sides of the semiconductor element. Such a structure is especially compact and may be used as two or t... | 09/02/2008 |
| 7416944 | Flash EEPROM device and method for fabricating the same In a flash EEPROM device, and method for fabricating the same, no bit line contact is made, thereby minimizing a design rule between a contact and a gate. Thus, cell size may be reduced. The flash EEPROM device includes a semiconductor substrate having an active are... | 08/26/2008 |
| 7414280 | Systems and methods for memory structure comprising embedded flash memory A memory structure that combines multiple embedded flash memory. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. In one aspect, the flash memory cells are stacked on top of the flash memory cells and the fl... | 08/19/2008 |
| 7414282 | Method of manufacturing a non-volatile memory device A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to... | 08/19/2008 |
| 7414297 | Capacitor constructions The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is form... | 08/19/2008 |
| 7411243 | Nonvolatile semiconductor device and method of fabricating the same A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface... | 08/12/2008 |
| 7391072 | Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which h... | 06/24/2008 |
| 7391078 | Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace... | 06/24/2008 |
| 7391076 | Non-volatile memory cells A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode pr... | 06/24/2008 |
| 7385244 | Flash memory devices with box shaped polygate structures A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching ... | 06/10/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| 7379321 | Memory cell and programmable logic having ferromagnetic structures exhibiting the extraordinary hall effect Memory cell structures make use of the extraordinary Hall effect (EHE) for increased data storage capacity. A memory cell has a ferromagnetic structure which includes at least a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer in between t... | 05/27/2008 |
| 7371638 | Nonvolatile memory cells having high control gate coupling ratios using grooved floating gates and methods of forming same A non-volatile memory cell includes a semiconductor substrate having a fin-shaped active region extending therefrom. A tunnel dielectric layer is provided, which extends on opposing sidewalls and an upper surface of the fin-shaped active region. A floating gate elec... | 05/13/2008 |
| 7371626 | Method for maintaining topographical uniformity of a semiconductor memory array A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer s... | 05/13/2008 |
| 7368781 | Contactless flash memory array A method for forming a contactless flash memory cell array is disclosed. According to an embodiment of the invention, a plurality of active regions is formed on a substrate. An insulating layer is then deposited over the active regions, and a portion of the insulati... | 05/06/2008 |
