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| Number | Title | Issue Date |
| 8188530 | Nonvolatile semiconductor memory device and method for manufacturing same A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction;... | 05/29/2012 |
| 8188531 | Dual gate of semiconductor device capable of forming a layer doped in high concentration over a recessed portion of substrate for forming dual gate with recess channel structure and method for manufacturing the same A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type Si... | 05/29/2012 |
| 8183617 | Injection method with Schottky source/drain An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and... | 05/22/2012 |
| 8183618 | Method for fabricating a charge trapping memory device A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process... | 05/22/2012 |
| 8178916 | Nonvolatile semiconductor storage device A semiconductor memory device includes: a semiconductor substrate; a plurality of device isolation regions being disposed in an upper-layer portion of the semiconductor substrate, and dividing the upper-layer portion into a plurality of semiconductor portions extend... | 05/15/2012 |
| 8169016 | Nonvolatile semiconductor memory device and method of manufacturing the same A plurality of conductive layers are stacked in a first region and a second region. A semiconductor layer is surrounded by the conductive layers in the first region, includes a columnar portion extending in a perpendicular direction with respect to a substrate. A ch... | 05/01/2012 |
| 8164134 | Semiconductor device Provided are a semiconductor device and a method of fabricating the same. At least one mold structure defining at least one first opening is formed on a substrate, wherein the mold structure comprises first mold patterns and second mold patterns that are sequentiall... | 04/24/2012 |
| 8159017 | Non-volatile memory device and method of manufacturing the same A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semic... | 04/17/2012 |
| 8154068 | Non-volatile semiconductor storage device and method of manufacturing the same Each of memory strings comprising: a first semiconductor layer having a pair of columnar portions extending in a vertical direction to a substrate and a joining portion formed to join lower ends of the pair of columnar portions; an electric charge accumulation layer... | 04/10/2012 |
| 8148766 | Nonvolatile memory cell A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting l... | 04/03/2012 |
| 8143661 | Memory cell system with charge trap A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown. | 03/27/2012 |
| 8143662 | Semiconductor device A semiconductor device comprising a first insulating film provided on a semiconductor substrate in a cell transistor region, a first conductive film provided on the first insulating film, an inter-electrode insulating film provided on the first conductive film, a se... | 03/27/2012 |
| 8138540 | Trench type non-volatile memory having three storage locations in one memory cell A non-volatile memory. The non-volatile memory comprises a substrate, a conductive layer, a charge storage layer, several first doped regions and several second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is located ... | 03/20/2012 |
| 8134197 | Nanowire transistor with surrounding gate One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crys... | 03/13/2012 |
| 8129774 | EEPROM with increased reading speed In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1... | 03/06/2012 |
| 8125015 | Nonvolatile memory devices Nonvolatile memory devices and methods of making the same are described. A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string sele... | 02/28/2012 |
| 8120089 | Non-volatile memory device and method for fabricating non-volatile memory device Provided are nonvolatile memory devices with a three-dimensional structure and methods of fabricating the same. The nonvolatile memory device includes conductive patterns three-dimensionally arranged on a semiconductor substrate, semiconductor patterns that extend f... | 02/21/2012 |
| 8120088 | Non-volatile memory cell and array Memory cells and arrays have reduced bit line resistance. An element conductor is disposed on the top of the bit line to reduce the resistance of the bit line while maintaining a shallow bit line junction so that 200 Ohm/square or lower sheet resistances are achieve... | 02/21/2012 |
| 8115244 | Transistor of volatile memory device with gate dielectric structure capable of trapping charges The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first co... | 02/14/2012 |
| 8106442 | NROM fabrication method A method of fabricating an oxide-nitride-oxide (ONO) layer in a memory cell to retain charge well in the nitride layer includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a top oxide layer, thereby causing oxyg... | 01/31/2012 |
| 8101988 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device includes a semiconductor substrate that includes a trench, a charge storage layer that is formed inside of the trench, a first gate that is formed above a side surface and a bottom surface of the trench, a second gate that i... | 01/24/2012 |
| 8093645 | Non-volatile semiconductor memory device A non-volatile semiconductor memory device includes a plurality of memory cell regions including a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, and a first insulating film formed in a region between any two adjacent bit ... | 01/10/2012 |
| 8093644 | Multiwalled carbon nanotube memory device A carbon nanotube based memory device comprises a set of three concentric carbon nanotubes having different diameters. The diameters of the three concentric carbon nanotubes are selected such that an inner carbon nanotube is semiconducting, and intershell electron t... | 01/10/2012 |
| 8084805 | Three-dimensional microelectronic devices including repeating layer patterns of different thicknesses A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cell... | 12/27/2011 |
| 8080842 | Nonvolatile memory device Disclosed is a nonvolatile memory device with cell and peripheral circuit regions confined on a substrate. Cell gate electrodes are arranged in the cell region while peripheral gate electrodes are arranged in the peripheral-circuit region. Each cell gate electrode i... | 12/20/2011 |
| 8076708 | Structures for and method of silicide formation on memory array and peripheral logic devices A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage t... | 12/13/2011 |
| 8076707 | Pseudo-nonvolatile direct-tunneling floating-gate device A semiconductor device is provided that uses a floating gate to store analog- and digital-valued information for periods of time measured in milliseconds to hours. Charge is added to and/or removed from the floating gate by means of direct electron tunneling through... | 12/13/2011 |
| 8076709 | Nonvolatile semiconductor memory device In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral su... | 12/13/2011 |
| 8072017 | Nonvolatile semiconductor memory device The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer,... | 12/06/2011 |
| 8067795 | Single poly EEPROM without separate control gate nor erase regions A single-poly EEPROM memory device comprises source and drain regions in a semiconductor body, a floating gate overlying a portion of the source and drain regions, which defines a source-to-floating gate capacitance and a drain-to-floating gate capacitance, wherein ... | 11/29/2011 |
| 8063427 | Finfet-based non-volatile memory device A non-volatile memory device on a substrate layer (2) comprises source and drain regions (3) and a channel region (4). The source and drain regions (3) and the channel region (4) are arranged in a semiconductor layer (20) on... | 11/22/2011 |
| 8039886 | Depletion-type NAND flash memory A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell t... | 10/18/2011 |
| 8035149 | Nonvolatile memory devices with oblique charge storage regions and methods of forming the same A nonvolatile memory device includes an active region defined by a device isolation layer in a semiconductor substrate, a word line passing over the active region and a charge storage region defined by a crossing of the active region and the word line and disposed b... | 10/11/2011 |
| 8030698 | Nonvolatile memory device Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers... | 10/04/2011 |
| 8022461 | Semiconductor device and method for fabricating semiconductor device A semiconductor device includes a plurality of bit lines repeatedly arranged with a same line width and pitch in a memory device region; a plurality of shunt lines arranged in a same layer as that of the plurality of bit lines, in parallel therewith, and with the sa... | 09/20/2011 |
| 8022460 | Nonvolatile semiconductor memory device An object is to provide a nonvolatile semiconductor memory device which is superior in writing property and charge holding property. A semiconductor substrate in which a channel formation region is formed between a pair of impurity regions is provided, and a first i... | 09/20/2011 |
| 8017986 | Semiconductor device A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which ... | 09/13/2011 |
| 8008700 | Non-volatile memory cell with embedded antifuse A nonvolatile memory device includes at least one memory cell which comprises a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion. ... | 08/30/2011 |
| 8004031 | Memory device transistors Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additi... | 08/23/2011 |
| 7989869 | Non-volatile memory devices having improved operational characteristics Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction. Devices may also include word lines that may cross over the active regions and... | 08/02/2011 |
