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| Number | Title | Issue Date |
| 8415733 | Semiconductor memory device and method for fabricating the same A semiconductor memory device has an asymmetric buried gate structure with a stepped top surface and a method for fabricating the same. The method for fabricating the semiconductor memory device includes: etching a predetermined region of a semiconductor substrate t... | 04/09/2013 |
| 8319265 | Semiconductor device with improved common source arrangement for adjacent non-volatile memory cells A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer an... | 11/27/2012 |
| 8217441 | Semiconductor constructions including gate arrays formed on partial SOI substrate The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. Th... | 07/10/2012 |
| 8174060 | Selective spacer formation on transistors of different classes on the same device A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a bloc... | 05/08/2012 |
| 8154067 | Selective spacer formation on transistors of different classes on the same device A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a bloc... | 04/10/2012 |
| 8106441 | Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher ... | 01/31/2012 |
| 8013378 | Memory device having additional selection transistors and main bit lines A semiconductor memory device has an element isolation region between rewrite units of memory cells. A plurality of memory cells are memory cell groups arranged in a row direction, and each memory cell group consists of (8×N) memory cells arranged in a row directio... | 09/06/2011 |
| 7872295 | Method of making flash memory cells and peripheral circuits having STI, and flash memory devices and computer systems having the same An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel b... | 01/18/2011 |
| 7804118 | Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher ... | 09/28/2010 |
| 7777267 | Manufacture method and structure of a nonvolatile memory The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate... | 08/17/2010 |
| 7683419 | Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher ... | 03/23/2010 |
| 7598559 | Semiconductor storage device, manufacturing method therefor, and portable electronic equipment A semiconductor storage device has a semiconductor layer having a first conductivity type region and two second conductivity type regions separated from each other by the first conductivity type region, a memory function body formed on a surface of the semiconductor... | 10/06/2009 |
| 7592661 | CMOS embedded high voltage transistor A circuit having a high voltage, drain-extended (DE) metal-oxide-semiconductor (MOS) transistor and method for fabricating the same are provided. Generally, the circuit includes an n-channel (NMOS) transistor having: (i) a source and drain formed in a substrate, the... | 09/22/2009 |
| 7544988 | Semiconductor integrated circuit device and a method of manufacturing the same The memory cell transistor includes, in a first well region, a pair of memory electrodes, one of which serves as source electrode and the other serves as drain electrode and a channel region interposed between the pair of memory electrodes. There is, on a channel re... | 06/09/2009 |
| 7525145 | Semiconductor integrated circuit device and a method of manufacturing the same The memory cell transistor includes, in a first well region, a pair of memory electrodes, one of which serves as source electrode and the other serves as drain electrode and a channel region interposed between the pair of memory electrodes. There is, on a channel re... | 04/28/2009 |
| 7511328 | Semiconductor device having raised cell landing pad and method of fabricating the same A semiconductor device and method of manufacturing the same having pad extending parts, the semiconductor device includes an isolation layer that defines an active region and a gate electrode which traverses the active region. A source region is provided in the acti... | 03/31/2009 |
| 7427793 | Sacrificial self-aligned interconnect structure A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and ... | 09/23/2008 |
| 7420237 | Capacitor element A capacitor element is provided which is composed of a lower electrode, an upper electrode formed in opposing relation to the lower electrode, and a capacitor dielectric film made of a ferroelectric material or a high dielectric material and formed between the lower... | 09/02/2008 |
| 7414297 | Capacitor constructions The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is form... | 08/19/2008 |
| 7411836 | Method of operating non-volatile memory A method of operating a non-volatile memory comprising a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer clos... | 08/12/2008 |
| 7408218 | Semiconductor device having plural dram memory cells and a logic circuit A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher ... | 08/05/2008 |
| 7405439 | Memory cell structure and semiconductor memory device A memory cell structure comprises a first memory capacitor that is arranged in a first local area, and includes a first lower electrode, a first upper electrode, and a first dielectric oxide film interposed between the first lower electrode and the first upper elect... | 07/29/2008 |
| 7382014 | Semiconductor device with capacitor suppressing leak current A semiconductor device with a capacitor includes a lower electrode, a dielectric and an upper electrode on the dielectric layer. The dielectric layer including more than one polycrystalline tantalum oxide layer and more than one separation layer, wherein the polycry... | 06/03/2008 |
| 7378739 | Capacitor and light emitting display using the same A capacitor including a polysilicon layer doped with impurities to be conductive, a first dielectric layer formed on the polysilicon layer, a first conductive layer formed on the first dielectric layer, a second dielectric layer formed on the first conductive layer,... | 05/27/2008 |
| 7375376 | Semiconductor display device and method of manufacturing the same A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from esca... | 05/20/2008 |
| 7368775 | Single transistor DRAM cell with reduced current leakage and method of manufacture A single transistor planar DRAM memory cell with improved charge retention and reduced current leakage and a method for forming the same, the method including providing a semiconductor substrate; forming a gate dielectric on the semiconductor substrate; forming a pa... | 05/06/2008 |
| 7358172 | Poly filled substrate contact on SOI structure Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next... | 04/15/2008 |
| 7355236 | Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof. The non-volatile floating gate memory cell comprises a semiconductor substrate of a first conductivity type. A first region of a second conductivity type different... | 04/08/2008 |
| 7352646 | Semiconductor memory device and method of arranging a decoupling capacitor thereof A semiconductor memory device with improved operational performance by reducing the level variation of first and second power voltages applied to a sense amplifier by efficiently locating a decoupling capacitor. The decoupling capacitor is arranged on an empty regio... | 04/01/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7339222 | Method for determining wordline critical dimension in a memory array and related structure According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between tw... | 03/04/2008 |
| 7339231 | Semiconductor device and an integrated circuit card There is provided a technology capable of enhancing reliability in rewrite of storage information in a nonvolatile memory while checking an increase in area of a memory array thereof. With a memory array configuration, individual bit lines are connected to two memor... | 03/04/2008 |
| 7332393 | Method of fabricating a cylindrical capacitor A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate... | 02/19/2008 |
| 7329918 | Semiconductor memory device including storage nodes and resistors and method of manufacturing the same A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on ... | 02/12/2008 |
| 7326990 | Semiconductor device and method for fabricating the same A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least on... | 02/05/2008 |
| 7323708 | Phase change memory devices having phase change area in porous dielectric layer A phase change memory device includes a lower electrode and a porous dielectric layer having fine pores on the lower electrode. A phase change layer is provided in the fine pores of the porous dielectric layer. An upper electrode is provided on the phase change laye... | 01/29/2008 |
| 7320920 | Non-volatile flash memory device having at least two different channel concentrations and method of fabricating the same In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a ch... | 01/22/2008 |
| 7321150 | Semiconductor device precursor structures to a double-sided capacitor or a contact A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least one opening in an insulating layer on a semiconductor wafer. A first c... | 01/22/2008 |
| 7319254 | Semiconductor memory device having resistor and method of fabricating the same A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A stor... | 01/15/2008 |
| 7307332 | Semiconductor device and method for fabricating the same The semiconductor device comprises a gate electrode 112 formed over a semiconductor substrate 10, a sidewall spacer 116 formed on the sidewall of the gate electrode 112, a sidewall spacer 144 formed on the side wall of the gate ele... | 12/11/2007 |
