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Class 257/303 - Stacked capacitor


Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein the trench capacitor device contains
No. of patents: 967
Last issue date: 05/29/2012


                    25  
NumberTitleIssue Date
4794563Semiconductor memory device having a high capacitance storage capacitor
This invention provides a semiconductor memory device for an integrated circuit comprising a semiconductor substrate of a first conductivity type, a field insulation layer on the semiconductor substrate, and a switch. This switch includes a gate insulatio...
12/27/1988
4786954Dynamic ram cell with trench surrounded switching element
A semiconductor memory device has a semiconductor substrate of one conductivity type in which a plurality of memory cells are formed, each of the plurality of memory cells including at least one capacitor and having a trench which is formed from one major...
11/22/1988
4685197Fabricating a stacked capacitor
The present invention provides a structure and method for fabricating that structure which provides increased capacitance over the prior art while occupying a minimum of surface area of the integrated circuit. The present invention accomplishes this by in...
08/11/1987
4646118Semiconductor memory device
A semiconductor memory device, such as a MOS dynamic RAM device, having memory cells each comprising a transfer gate transistor and a capacitor. The capacitor is a so-called groove-type capacitor and has a conductive layer formed on an insulation film att...
02/24/1987
4329704MOS Random access memory with buried storage capacitor
A one transistor, one capacitance type dynamic MOS.RAM is provided with a buried storage capacitor and a planar transfer electrode. The MOS.RAM is, therefore, characterized by a small size of the memory cells and a simple production process. One process f...
05/11/1982
4163243One-transistor memory cell with enhanced capacitance
A one-transistor memory cell is provided in which the depletion-layer capacitance of an MOS capacitor is increased by locally enhancing the substrate dopant concentration. In preferred embodiments the substrate may also be doped adjacent to the substrate-...
07/31/1979
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