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| Number | Title | Issue Date |
| 7446365 | Fabricated layered capacitor for a digital-to-analog converter A fabricated layered capacitor having three layers is provided. The first bottom layer comprises a first bottom plate portion, the second middle layer comprises a first top plate portion, and the third top layer comprises a second bottom plate portion of the layered... | 11/04/2008 |
| 7442981 | Capacitor of semiconductor device and method of fabricating the same Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is ... | 10/28/2008 |
| 7442976 | DRAM cells with vertical transistors The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the s... | 10/28/2008 |
| 7436014 | Method of fabricating storage capacitor in semiconductor memory device, and storage capacitor structure A storage capacitor has a double cylinder type structure, with a small cylinder in a lower part thereof and a cylindrical lower electrode structure disposed on the cylindrical contact plug. A method of fabricating the storage capacitor includes: forming a contact ho... | 10/14/2008 |
| 7436016 | MIM capacitor with a cap layer over the conductive plates A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bott... | 10/14/2008 |
| 7432545 | Semiconductor device A capacity element with a simple configuration exhibits excellent production reliability. A semiconductor device 100 includes a capacity element consisting of a lower electrode 102, an SiCN film 107 and an upper electrode 113. In an insul... | 10/07/2008 |
| 7432597 | Semiconductor device and method of manufacturing the same In a semiconductor device including a memory region and a logic region, one or more of a plurality of logic transistor connection plugs, buried in a first insulating layer and connected to a diffusion layer of a logic transistor, are left unconnected to a first inte... | 10/07/2008 |
| 7427793 | Sacrificial self-aligned interconnect structure A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and ... | 09/23/2008 |
| 7425724 | Memory device and method of production and method of use of same and semiconductor device and method of production of same A memory device able to be produced without requiring high precision alignment, a method of production of the same, and a method of use of a memory device produced in this way, wherein a peripheral circuit portion (first semiconductor portion) formed by a first mini... | 09/16/2008 |
| 7416952 | Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayer A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal n... | 08/26/2008 |
| 7416953 | Vertical MIM capacitors and method of fabricating the same A method of fabricating a vertical MIM capacitor. An insulation layer is formed on the substrate. The insulation layer is patterned to form an opening in a predetermined area of a core electrode. Then, the opening is filled to form a sacrificial plug. Subsequently, ... | 08/26/2008 |
| 7414297 | Capacitor constructions The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is form... | 08/19/2008 |
| 7411256 | Semiconductor integrated circuit device capacitive node interconnect A semiconductor integrated circuit device is provided, which involves inhibiting a pattern change in the node interconnect and an increase of number of manufacturing process, when the capacitor is additionally installed in the SRAM, while providing higher reliabilit... | 08/12/2008 |
| 7405438 | Capacitor constructions and semiconductor structures The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is ... | 07/29/2008 |
| 7402488 | Method of manufacturing a semiconductor memory device A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of t... | 07/22/2008 |
| 7402860 | Method for fabricating a capacitor The present invention relates to a method of fabricating a capacitor in a semiconductor substrate. The capacitor is fabricated such that the capacitor comprises: a trench inside a substrate, the trench having a lower region and an upper region, wherein the trench's ... | 07/22/2008 |
| 7397078 | Non-volatile semiconductor memory A non-volatile semiconductor memory comprising at least one EPROM/EEPROM memory cell that includes a floating gate transistor and a coupling capacitor, said floating gate transistor comprising a field effect transistor and a polysilicon layer, the coupling capacitor... | 07/08/2008 |
| 7382012 | Reducing parasitic capacitance of MIM capacitor in integrated circuits by reducing effective dielectric constant of dielectric layer A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value ov... | 06/03/2008 |
| 7375376 | Semiconductor display device and method of manufacturing the same A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from esca... | 05/20/2008 |
| 7365386 | Semiconductor device and method of manufacturing the semiconductor device A semiconductor device having improved reliability is provided. The semiconductor device has a pixel portion. The pixel portion has a TFT and a storage capacitor. The TFT and the storage capacitor has a semiconductor layer which includes first and second regions for... | 04/29/2008 |
| 7365412 | Vertical parallel plate capacitor using spacer shaped electrodes and method for fabrication thereof A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalls of the aperture. A pair of capacitor... | 04/29/2008 |
| 7364979 | Capcitor with single crystal tantalum oxide layer and method for fabricating the same A capacitor and a method for fabricating the same are provided. The capacitor includes: a substrate; an inter-layer insulation layer formed over the substrate and including a contact hole; a storage node formed over the inter-layer insulation layer and filled into t... | 04/29/2008 |
| 7361599 | Integrated circuit and method A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch. ... | 04/22/2008 |
| 7361950 | Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capac... | 04/22/2008 |
| 7358557 | Capacitor for semiconductor device and method of forming the same A capacitor for a semiconductor device includes a lower electrode, a dielectric layer formed on a lower electrode, and an upper electrode formed on the dielectric layer. The lower electrode includes a first layer having a cylindrical shape and a mesh second layer fo... | 04/15/2008 |
| 7358556 | SRAM cell structure and manufacturing method thereof A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an openi... | 04/15/2008 |
| 7358172 | Poly filled substrate contact on SOI structure Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next... | 04/15/2008 |
| 7358133 | Semiconductor device and method for making the same A method for forming a semiconductor device is provided. The method comprises providing a substrate with recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed.... | 04/15/2008 |
| 7355880 | Soft error resistant memory cell and method of manufacture A semiconductor device memory cell (100) can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell (100) can include a first inverter (102) and second inverter (104) arranged in a cross-coupled configuration. A ... | 04/08/2008 |
| 7355232 | Memory devices with dual-sided capacitors A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the die... | 04/08/2008 |
| 7355288 | Low fabrication cost, high performance, high reliability chip scale package The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elast... | 04/08/2008 |
| 7351285 | Method and system for forming a variable thickness seed layer A method and system for forming a variable thickness seed layer on a substrate for a subsequent metal electrochemical plating process, where the seed layer thickness profile improves uniformity of the electroplated metal layer compared to when using a constant thick... | 04/01/2008 |
| 7352022 | Capacitor having a dielectric layer that reduces leakage current and a method of manufacturing the same A capacitor having a dielectric layer including a composite oxide, the composite oxide including a transition metal and including a lanthanide group element, a memory device including the same and a method of manufacturing the capacitor are provided. The transition ... | 04/01/2008 |
| 7352023 | Constructions comprising hafnium oxide The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is provided, and first reaction conditions are utilized to form hafnium-containing seed material in a desired crysta... | 04/01/2008 |
| 7348616 | Ferroelectric integrated circuit devices having an oxygen penetration path Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part o... | 03/25/2008 |
| 7348623 | Semiconductor device including a MIM capacitor A semiconductor device includes: a semiconductor substrate; a first wiring formed above the semiconductor substrate with a first insulating film interposed therebetween; an MIM capacitor formed above the first insulating film; a second insulating film formed to cove... | 03/25/2008 |
| 7348661 | Array capacitor apparatuses to filter input/output signal An apparatus for filtering noise from an input/output (I/O) signal is disclosed. In various embodiments, the apparatus may be an array capacitor, and may be disposed between an electronic package and an underlying substrate such as a printed circuit board. ... | 03/25/2008 |
| 7345333 | Double sided container process used during the manufacture of a semiconductor device A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is prov... | 03/18/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7342292 | Capacitor assembly having a contact electrode encircling or enclosing in rectangular shape an effective capacitor area A capacitor assembly has a substrate, a first conductive auxiliary layer on the substrate, a capacitor dielectric, a second conductive auxiliary layer and a contact electrode. Thereby the first conductive auxiliary layer is connected to the capacitor dielectric with... | 03/11/2008 |
