Class 257/297 - With means for preventing charge leakage due to minority carrier generation (e.g., alpha generated soft error protection or "dark current" leakage protection)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein the device further includes means
No. of patents: 260
Last issue date: 03/06/2012

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Number	Title	Issue Date
8129771	Semiconductor memory device In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer in the word line direction than in the bit line direction) including first and second driver MOS transistor...	03/06/2012
8115243	Surround gate access transistors with grown ultra-thin bodies A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching...	02/14/2012
7919800	Capacitor-less memory cells and cell arrays A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is form...	04/05/2011
7791123	Soft error protection structure employing a deep trench A deep trench containing a doped semiconductor fill portion having a first conductivity type doping and surrounded by a buried plate layer having a second conductivity type doping at a lower portion is formed in a semiconductor layer having a doping of the first con...	09/07/2010
7700985	Ferroelectric memory using multiferroics Ferroelectric memory using multiferroics is described. The multiferroic memory includes a substrate having a source region, a drain region and a channel region separating the source region and the drain region. An electrically insulating layer is adjacent to the sou...	04/20/2010
7514737	Semiconductor memory device In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer in the word line direction than in the bit line direction) including first and second driver MOS transistor...	04/07/2009
7414279	Semiconductor device with improved overlay margin and method of manufacturing the same Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation...	08/19/2008
7411238	Semiconductor integrated circuit device and a method of manufacturing the same In order to improve the soft error resistance of a memory cell of an SRAM without increasing its chip size in deep through-holes formed by perforating a silicon oxide film, there is a silicon nitride film and a silicon oxide film, a capacitor element having a TIN fi...	08/12/2008
7388274	Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an act...	06/17/2008
7378739	Capacitor and light emitting display using the same A capacitor including a polysilicon layer doped with impurities to be conductive, a first dielectric layer formed on the polysilicon layer, a first conductive layer formed on the first dielectric layer, a second dielectric layer formed on the first conductive layer,...	05/27/2008
7375376	Semiconductor display device and method of manufacturing the same A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from esca...	05/20/2008
7342276	Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme...	03/11/2008
7332390	Semiconductor memory device and fabrication thereof A semiconductor memory device and fabrication method thereof. In a semiconductor memory device, each memory cell comprises a deep trench and a capacitor disposed on the lower portion thereof. A collar oxide layer having a first second sidewalls is disposed on the de...	02/19/2008
7326990	Semiconductor device and method for fabricating the same A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least on...	02/05/2008
7323708	Phase change memory devices having phase change area in porous dielectric layer A phase change memory device includes a lower electrode and a porous dielectric layer having fine pores on the lower electrode. A phase change layer is provided in the fine pores of the porous dielectric layer. An upper electrode is provided on the phase change laye...	01/29/2008
7319254	Semiconductor memory device having resistor and method of fabricating the same A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A stor...	01/15/2008
7315075	Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an act...	01/01/2008
7307304	Ferroelectric materials and ferroelectric memory device made therefrom A ferroelectric material includes a compound of formula (I): (Pb1−x−zBazAx)(ByZr1−y)O3, (I) wherein 0≦x≦0.1, 0≦y≦0.020, 0.15≦z≦0.35, with the proviso that y...	12/11/2007
7301219	Electrically erasable programmable read only memory (EEPROM) cell and method for making the same An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to th...	11/27/2007
7298000	Conductive container structures having a dielectric cap Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conducti...	11/20/2007
7288806	DRAM arrays The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact...	10/30/2007
7276725	Bit line barrier metal layer for semiconductor device and process for preparing the same The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose a...	10/02/2007
7262107	Capacitor structure for a logic process A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used ...	08/28/2007
7262104	Selective channel implantation for forming semiconductor devices with different threshold voltages Multiple semiconductor devices are formed with different threshold voltages. According to one exemplary implementation, first and second semiconductor devices are formed and doped differently, resulting in different threshold voltages for the first and second semico...	08/28/2007
7256437	Semiconductor storage device which includes a hydrogen diffusion inhibiting layer The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a h...	08/14/2007
7253465	Semiconductor integrated circuit device and manufacturing method thereof In a dual polymetal gate electrode, the contact resistance at the interface of silicon films increases due to mutual-diffusion of impurities of p-type and n-type silicon films through a refractory metal and metal nitride deposited thereon. A way of inhibiting the ph...	08/07/2007
7244982	Semiconductor device using a conductive film and method of manufacturing the same A semiconductor device has a capacitive element including a first conductive film formed on the bottom and wall surfaces of an opening formed in an insulating film on a substrate, a dielectric film formed on the first conductive film, and a second conductive film fo...	07/17/2007
7238544	Imaging with gate controlled charge storage A pixel cell comprises a photo-conversion device for generating charge and a gate controlled charge storage region for storing photo-generated charge under control of a control gate. The charge storage region can be a single CCD stage having a buried channel to obta...	07/03/2007
7235837	Technique to control tunneling currents in DRAM capacitors, cells, and devices Structures and methods are provided for the use with PMOS devices. Materials with large electron affinities or work functions are provided for structures such as gates. A memory cell is provided that utilizes materials with work functions larger than n-type doped po...	06/26/2007
7233516	Semiconductor device and method for fabricating the same A semiconductor device includes a first DRAM section formed on a semiconductor substrate and composed of a plurality of first memory cells and a second DRAM section formed on the semiconductor substrate and composed of a plurality of second memory cells. The operati...	06/19/2007
7212432	Resistive memory cell random access memory device and method of fabrication A resistive memory cell random access memory device and method for fabrication. In one embodiment, the invention relates to a resistive memory cell random access memory device comprising a plurality of first current lines; a plurality of second current lines; a plur...	05/01/2007
7208788	Semiconductor device and manufacturing method thereof A semiconductor device and a manufacturing method thereof in which the peripheral length of an aperture and the mechanical strength of cylinders in a cell can be increased without changing the occupation rate of patterns in the cell. By forming a slit in the middle ...	04/24/2007
7208794	High-density NROM-FINFET Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence ...	04/24/2007
7205599	Devices having improved capacitance A capacitor formed by a process using only two deposition steps and a dielectric formed by oxidizing a metal layer in an electrolytic solution. The capacitor has first and second conductive plates and a dielectric is formed from the first conductive plate. ...	04/17/2007
7205241	Method for manufacturing semiconductor device with contact body extended in direction of bit line Methods for manufacturing semiconductor devices with contact bodies extended in a direction of a bit line to increase the contact area between a contact body and a storage electrode is provided. In one aspect a method includes forming gate lines on a semiconductor s...	04/17/2007
7202538	Ultra low leakage MOSFET transistor A MOSFET transistor structure is formed in a substrate of semiconductor material having a first conductivity type. The MOSFET transistor structure includes an active region that is surrounded by a perimeter isolation dielectric material formed in the substrate to de...	04/10/2007
7199415	Conductive container structures having a dielectric cap Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conducti...	04/03/2007
7180114	Semiconductor device A semiconductor device includes a silicon substrate having a film thickness smaller than a maximum range of a particle generated by a nuclear reaction between a fast neutron and a silicon atom, and a semiconductor element formed on a surface of the silicon substrate...	02/20/2007
7164294	Method for forming programmable logic arrays using vertical gate transistors One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each including a plurality of logic cells interconnected to implement a logical fu...	01/16/2007
7145195	Semiconductor memory device and method of manufacturing the same A semiconductor device comprises a semiconductor substrate including an isolation region defining an active area with a plurality of source/drain regions. A contact pad layer is formed on the semiconductor substrate and includes gate line structures, first contact p...	12/05/2006

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Class 257/297 - With means for preventing charge leakage due to minority carrier generation (e.g., alpha generated soft error protection or "dark current" leakage protection)