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| Number | Title | Issue Date |
| 7358144 | Method for fabricating semiconductor device A method for fabricating a semiconductor device includes forming first, second, and third device structures in a semiconductor substrate. Each device structure includes a first film, a second film over the first film, and a third film over the second film. The first... | 04/15/2008 |
| 7358555 | Semiconductor device While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. | 04/15/2008 |
| 7358590 | Semiconductor device and driving method thereof A semiconductor device includes a memory with a simple structure, an inexpensive semiconductor device, a manufacturing method and a driving method thereof. One feature is that, in a memory which has a layer including an organic compound as a dielectric, by applying ... | 04/15/2008 |
| 7358133 | Semiconductor device and method for making the same A method for forming a semiconductor device is provided. The method comprises providing a substrate with recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed.... | 04/15/2008 |
| 7358172 | Poly filled substrate contact on SOI structure Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next... | 04/15/2008 |
| 7359273 | Semiconductor memory device having layout for minimizing area of sense amplifier region and word line driver region A semiconductor memory device has a layout that minimizes the area required for sense amplifier and word line driver regions. In the semiconductor memory device of the present invention, decoding drivers are arranged in sense amplifier regions. Further, the wiring f... | 04/15/2008 |
| 7358554 | Semiconductor manufacturing apparatus for modifying-in-film stress of thin films, and product formed thereby An apparatus for depositing a thin film on a substrate and product produced thereby are disclosed. In particular, deposition of the thin film is carried out on the substrate having an applied pressure. This applied pressure flexes the substrate to reduce in-plane st... | 04/15/2008 |
| 7355231 | Memory circuitry with oxygen diffusion barrier layer received over a well base A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semic... | 04/08/2008 |
| 7356795 | Semiconductor integrated circuit device and method for designing the same A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one ... | 04/08/2008 |
| 7355230 | Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access ... | 04/08/2008 |
| 7355246 | Memory cell without halo implant Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with cha... | 04/08/2008 |
| 7355232 | Memory devices with dual-sided capacitors A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the die... | 04/08/2008 |
| 7354872 | Hi-K dielectric layer deposition methods Methods of forming a high dielectric constant dielectric layer are disclosed including providing a process chamber including a holder for supporting a substrate, introducing a first gas comprising a high dielectric constant (Hi-K) dielectric precursor and an oxygen ... | 04/08/2008 |
| 7355265 | Semiconductor integrated circuit A semiconductor integrated circuit comprising a power supply wiring and a ground wiring and a decoupling capacitor formed between the power supply wiring and the ground wiring, wherein at least one electrode of the decoupling capacitor consists of a shield layer for... | 04/08/2008 |
| 7354793 | Method of forming a PCRAM device incorporating a resistance-variable chalocogenide element A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method. ... | 04/08/2008 |
| 7354821 | Methods of fabricating trench capacitors with insulating layer collars in undercut regions Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the firs... | 04/08/2008 |
| 7353481 | Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a... | 04/01/2008 |
| 7352060 | Multilayer wiring substrate for providing a capacitor structure inside a multilayer wiring substrate A multilayer wiring substrate for providing a capacitor structure inside a multilayer wiring structure is disclosed. The multilayer wiring substrate includes a dielectric layer including a resin material mixed with an inorganic filler, wherein the inorganic filler i... | 04/01/2008 |
| 7352026 | EEPROM cell and EEPROM device with high integration and low source resistance and method of manufacturing the same Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a fir... | 04/01/2008 |
| 7351991 | Methods for forming phase-change memory devices Phase-change memory devices include a phase-change material layer and a first electrode having a contact area therebetween. The contact area extends into a recess of the first electrode to provide current density concentration. ... | 04/01/2008 |
| 7352022 | Capacitor having a dielectric layer that reduces leakage current and a method of manufacturing the same A capacitor having a dielectric layer including a composite oxide, the composite oxide including a transition metal and including a lanthanide group element, a memory device including the same and a method of manufacturing the capacitor are provided. The transition ... | 04/01/2008 |
| 7348599 | Semiconductor device and manufacturing method thereof A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at l... | 03/25/2008 |
| 7348618 | Flash memory cell having reduced floating gate to floating gate coupling According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate sta... | 03/25/2008 |
| 7348243 | Semiconductor device and method for fabricating the same A transistor and a method for fabricating the same is disclosed, to uniformly provide impurity ions in impurity areas, and to prevent a short channel effect, in which the method for fabricating the transistor includes steps of forming a plurality of channel ion impl... | 03/25/2008 |
| 7349234 | Magnetic memory array A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for r... | 03/25/2008 |
| 7349195 | Thin film capacitor and method for manufacturing the same The present invention provides the steps of (a) forming a first electrode on a substrate via an adhesion enhancing layer, (b) forming a capacitor insulating film containing a laminated film, in which an amorphous dielectric film and a polycrystalline dielectric film... | 03/25/2008 |
| 7349035 | Thin film transistor array substrate having particular patterned electrode A thin film transistor array substrate including a substrate, scan lines, data lines, thin film transistors, pixel electrodes, common lines and a patterned upper electrode is provided. The scan lines and the data lines are disposed over the substrate to define pixel... | 03/25/2008 |
| 7348616 | Ferroelectric integrated circuit devices having an oxygen penetration path Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part o... | 03/25/2008 |
| 7348624 | Semiconductor device including a capacitor element A semiconductor device having a capacitor including a first electrode, a second electrode and an insulator. The semiconductor device includes first layers and second layers laminated alternately. The first layers each includes lines of the first electrode and lines ... | 03/25/2008 |
| 7348619 | Ferroelectric memory arrangement A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelec... | 03/25/2008 |
| 7349232 | 6FDRAM cell design with 3F-pitch folded digitline sense amplifier The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality o... | 03/25/2008 |
| 7349250 | Semiconductor device The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first... | 03/25/2008 |
| 7348209 | Resistance variable memory device and method of fabrication Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least on... | 03/25/2008 |
| 7348653 | Resistive memory cell, method for forming the same and resistive memory array using the same A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly pa... | 03/25/2008 |
| 7348675 | Microcircuit fabrication and interconnection Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to elec... | 03/25/2008 |
| 7349251 | Integrated memory circuit arrangement A memory circuit arrangement includes a switching element per column that can be used to connect or disconnect two bit lines for memory cells of a column. The switching element leads to a reduction of the chip area and/or to an improvement in the electronic properti... | 03/25/2008 |
| 7348194 | Electrode compositions containing carbon nanotubes for solid electrolyte capacitors An improved capacitor with an anode with an anode wire and an oxide layer on the surface of the anode. A cathode layer is exterior to the oxide layer. A carbon conductive layer is exterior to the cathode layer wherein the cathode layer comprises 5-75 wt % resin and ... | 03/25/2008 |
| 7348623 | Semiconductor device including a MIM capacitor A semiconductor device includes: a semiconductor substrate; a first wiring formed above the semiconductor substrate with a first insulating film interposed therebetween; an MIM capacitor formed above the first insulating film; a second insulating film formed to cove... | 03/25/2008 |
| 7348620 | Forming phase change memories Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the... | 03/25/2008 |
| 7345332 | Semiconductor constructions The invention includes a method of forming a planarized surface over a semiconductor substrate. A substrate is provided which includes a memory array region and a peripheral region proximate the memory array region. The memory array region has a higher average eleva... | 03/18/2008 |
