Celebrity Inventors
Mark Twain (Samuel L. Clemens) received Patent No. 121,992 for "An Improvement in Adjustable and Detachable Straps for Garments." He later received two more patents: one for a self-pasting scrapbook and one for a game to help players remember important historical dates.
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| Number | Title | Issue Date |
| 7375389 | Semiconductor device having a capacitor-under-bitline structure and method of manufacturing the same Provided are semiconductor devices having a system-on-chip (SOC) configuration that combines both a capacitor-based cell-array memory region and one or more MOS core/peripheral circuit/logic regions on a single chip and a method for manufacturing such devices. The m... | 05/20/2008 |
| 7371588 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device includes: forming a circuit element on a semiconductor substrate; forming a first insulation film on top to cover the circuit element; forming a first electrode on top; forming a ferroelectric film on the first electr... | 05/13/2008 |
| 7371645 | Method of manufacturing a field effect transistor device with recessed channel and corner gate device Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A pr... | 05/13/2008 |
| 7372101 | Sub-lithographics opening for back contact or back gate A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the t... | 05/13/2008 |
| 7372093 | DRAM memory with vertically arranged selection transistors The invention relates to a semiconductor memory, particularly a DRAM, in which the memory cells in each case have a trench capacitor arranged in a lower area of a trench hole and a vertical selection transistor which is formed adjoining an upper area of the trench h... | 05/13/2008 |
| 7372092 | Memory cell, device, and system A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with ad... | 05/13/2008 |
| 7371647 | Methods of forming transistors The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nit... | 05/13/2008 |
| 7372090 | Magnetic random access memory device and method of forming the same Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a m... | 05/13/2008 |
| 7372091 | Selective epitaxy vertical integrated circuit components Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of t... | 05/13/2008 |
| 7372166 | Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated ... | 05/13/2008 |
| 7368350 | Memory cell arrays and methods for producing memory cell arrays A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask la... | 05/06/2008 |
| 7368775 | Single transistor DRAM cell with reduced current leakage and method of manufacture A single transistor planar DRAM memory cell with improved charge retention and reduced current leakage and a method for forming the same, the method including providing a semiconductor substrate; forming a gate dielectric on the semiconductor substrate; forming a pa... | 05/06/2008 |
| 7368776 | Semiconductor device comprising a highly-reliable, constant capacitance capacitor A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. ... | 05/06/2008 |
| 7368825 | Power semiconductor device The present invention is directed to a power semiconductor device in which a control circuit controls a power switching element, comprising: a semiconductor substrate having a front surface and a back surface; a capacitor disposed on the front surface side of the se... | 05/06/2008 |
| 7369424 | Programmable memory cell and operation method A memory array including a plurality of programmable memory cells, a plurality of column lines and a plurality of row lines is introduced. Each of the programmable memory cells is coupled to corresponding one of the column lines and corresponding one of the row line... | 05/06/2008 |
| 7368699 | Segmented image intensifier According to some embodiments of the invention, an image intensifier is provided. The image intensifier comprises a layer of electrically isolated electrode segments each able to receive an electrical potential independently of the other electrode segments. The elec... | 05/06/2008 |
| 7368774 | Capacitor and its manufacturing method, ferroelectric memory device, actuator, and liquid jetting head A capacitor includes a lower electrode, a first dielectric film composed of lead zirconate titanate niobate formed above the lower electrode, a second dielectric film composed of lead zirconate titanate or lead zirconate titanate niobate with a Nb composition smalle... | 05/06/2008 |
| 7368344 | Methods of reducing floating body effect Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a prefe... | 05/06/2008 |
| 7368752 | DRAM memory cell A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/... | 05/06/2008 |
| 7367119 | Method for forming a reinforced tip for a probe storage device Systems and methods in accordance with the present invention can include a tip contactable with a media. In an embodiment, the tip comprises a substantially hollow structure formed of a metal. The tip can be formed by depositing a first metal layer over silicon ther... | 05/06/2008 |
| 7368352 | Semiconductor devices having transistors with vertical channels and method of fabricating the same In a semiconductor device and a method of fabricating the same, a vertical channel transistor has a cell occupation area of 4F2. The semiconductor device comprises: a cell array region having a plurality of unit cells, each unit cell having a cell occupat... | 05/06/2008 |
| 7365385 | DRAM layout with vertical FETs and method of formation DRAM cell arrays having a cell area of less than about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the subst... | 04/29/2008 |
| 7365384 | Trench buried bit line memory devices and methods thereof A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermo... | 04/29/2008 |
| 7364937 | Vertical elevated pore phase change memory A vertical elevated pore structure for a phase change memory may include a pore with a lower electrode beneath the pore contacting the phase change material in the pore. The lower electrode may be made up of a higher resistivity lower electrode and a lower resistivi... | 04/29/2008 |
| 7364974 | Double gate FET and fabrication process A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulatin... | 04/29/2008 |
| 7365383 | Method of forming an EPROM cell and structure therefor An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate. ... | 04/29/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7365412 | Vertical parallel plate capacitor using spacer shaped electrodes and method for fabrication thereof A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalls of the aperture. A pair of capacitor... | 04/29/2008 |
| 7365433 | High-frequency semiconductor device and method of manufacturing the same The object of the present invention is to implement an enhancement in a noise eliminating characteristic of a wiring compatibly with promotion of microfabrication and simplification of a manufacturing process. Upper and side surfaces of a wiring (6) for trans... | 04/29/2008 |
| 7361548 | Methods of forming a capacitor using an atomic layer deposition process Methods for forming a capacitor using an atomic layer deposition process include providing a reactant including an aluminum precursor onto a substrate to chemisorb a portion of the reactant to a surface of the substrate. The substrate has an underlying structure inc... | 04/22/2008 |
| 7361537 | Method of fabricating recess channel array transistor A method of fabricating a recess channel array transistor is disclosed. An impurity region is formed in a semiconductor substrate. Then, a polysilicon layer is formed on the semiconductor substrate, both of which are then etched to form a trench that defines an acti... | 04/22/2008 |
| 7361959 | CMOS circuits including a passive element having a low end resistance The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, ca... | 04/22/2008 |
| 7362401 | In plane switching liquid crystal displaying apparatus for improved luminance including a thin film transistor array substrate An In Plane Switching (IPS) liquid crystal displaying apparatus includes a TFT array substrate, an opposite substrate opposed to the TFT array substrate and a liquid crystal interposed between the TFT array substrate and the opposite substrate. The TFT array substra... | 04/22/2008 |
| 7361552 | Semiconductor integrated circuit including a DRAM and an analog circuit A semiconductor device including an interlayer insulation film formed on a substrate so as to cover first and second regions defined on the substrate, and a capacitor formed over the interlayer insulation film in the first region, wherein the interlayer insulation f... | 04/22/2008 |
| 7362615 | Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in t... | 04/22/2008 |
| 7361550 | Methods of fabricating semiconductor memory devices including electrode contact structures having reduced contact resistance A semiconductor memory device includes a semiconductor substrate having an active region therein, an insulating layer on the substrate, and a lower electrode conductive pad extending through the insulating layer. The lower electrode conductive pad electrically conta... | 04/22/2008 |
| 7361583 | RF semiconductor devices and methods for fabricating the same RF semiconductor devices and methods of making the same are disclosed. In a disclosed method, a trench for defining an active region and an element isolation region is formed in a semiconductor substrate. One or more gate lines is then formed within the active regio... | 04/22/2008 |
| 7361587 | Semiconductor contact and nitride spacer formation system and method The present invention is a semiconductor contact formation system and methods that form contact insulation regions comprising multiple etch stop sublayers that facilitate formation of contacts. This contract formation process provides relatively small substrate conn... | 04/22/2008 |
| 7358555 | Semiconductor device While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. | 04/15/2008 |
| 7358554 | Semiconductor manufacturing apparatus for modifying-in-film stress of thin films, and product formed thereby An apparatus for depositing a thin film on a substrate and product produced thereby are disclosed. In particular, deposition of the thin film is carried out on the substrate having an applied pressure. This applied pressure flexes the substrate to reduce in-plane st... | 04/15/2008 |
