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| Number | Title | Issue Date |
| 7332761 | Method for fabricating capacitor of semiconductor device The present invention relates to a method for fabricating a capacitor of a semiconductor device. The semiconductor device includes: a bit line structure formed on a substrate and including stacked layers of a bit line, a hard mask and a spacer, the spacer formed alo... | 02/19/2008 |
| 7332764 | Metal-insulator-metal (MIM) capacitor and method of fabricating the same In a MIM capacitor, and method of fabricating the same, the MIM capacitor includes an interlayer insulating layer on a semiconductor substrate, a lower metal interconnection and a lower metal electrode in the interlayer insulating layer, an intermetal dielectric lay... | 02/19/2008 |
| 7332762 | Nonvolatile semiconductor memory A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above... | 02/19/2008 |
| 7332767 | High density memory devices having improved channel widths and cell size A memory device having decreased cell size and having transistors with increased channel widths. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a conductive layer to form a channel through the pillars. The current p... | 02/19/2008 |
| 7332393 | Method of fabricating a cylindrical capacitor A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate... | 02/19/2008 |
| 7332380 | Pattern design method and program of a semiconductor device including dummy patterns According to an aspect of the present invention, there is provided a pattern design method of a semiconductor device, including preparing design pattern data, separating a pattern region of a semiconductor device on the basis of the design pattern data into a dummy ... | 02/19/2008 |
| 7332418 | High-density single transistor vertical memory gain cell A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away f... | 02/19/2008 |
| 7332390 | Semiconductor memory device and fabrication thereof A semiconductor memory device and fabrication method thereof. In a semiconductor memory device, each memory cell comprises a deep trench and a capacitor disposed on the lower portion thereof. A collar oxide layer having a first second sidewalls is disposed on the de... | 02/19/2008 |
| 7332427 | Method of forming an interconnection line in a semiconductor device A method of forming an interconnection line in a semiconductor device includes forming an interlayer insulating layer on an underlying layer having a lower conductive layer, patterning the interlayer insulating layer to form an opening exposing the lower conductive ... | 02/19/2008 |
| 7332736 | Article comprising gated field emission structures with centralized nanowires and method for making the same This invention provides novel methods of fabricating novel gated field emission structures that include aligned nanowire electron emitters (individually or in small groups) localized in central regions within gate apertures. It also provides novel devices using nano... | 02/19/2008 |
| 7332389 | Selective polysilicon stud growth A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilico... | 02/19/2008 |
| 7333361 | Biosensor and sensing cell array using the same A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array inc... | 02/19/2008 |
| 7329919 | Non-volatile memory device and method of manufacturing the same A non-volatile memory device and a method of manufacturing the same where the non-volatile memory device is easily applicable to higher integration of a semiconductor device by reducing a cell size while assuring storage capacities required for operations of a devic... | 02/12/2008 |
| 7329918 | Semiconductor memory device including storage nodes and resistors and method of manufacturing the same A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on ... | 02/12/2008 |
| 7329548 | Integration processes for fabricating a conductive metal oxide gate ferroelectric memory transistor A method of fabricating a conductive metal oxide gate ferroelectric memory transistor includes forming an oxide layer a substrate and removing the oxide layer in a gate area; depositing a conductive metal oxide layer on the oxide layer and on the exposed gate area; ... | 02/12/2008 |
| 7329567 | Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemic... | 02/12/2008 |
| 7329916 | DRAM cell arrangement with vertical MOS transistors The invention is related to a DRAM cell arrangement with vertical MOS transistors. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors bel... | 02/12/2008 |
| 7329939 | Metal-insulator-metal capacitor and method of fabricating same A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive ... | 02/12/2008 |
| 7326612 | Method for fabricating a semiconductor structure A method is provided for fabricating a semiconductor structure, such as a DRAM memory cell, that includes an elevated region with at least one sidewall. The at least one sidewall is provided with an insulation layer. A mask layer is applied to the insulation layer. ... | 02/05/2008 |
| 7326613 | Methods of manufacturing semiconductor devices having elongated contact plugs A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewall... | 02/05/2008 |
| 7326950 | Memory device with switching glass layer A memory device, such as a PCRAM, including a chalcogenide glass backbone material with germanium telluride glass and methods of forming such a memory device. ... | 02/05/2008 |
| 7326982 | MRAM and method of manufacturing the same A magnetic memory device comprising, a magneto-resistance effect element that is provided at an intersection between a first write line and a second write line. And the magneto-resistance effect element having, an easy axis that extends in a direction of extension o... | 02/05/2008 |
| 7326983 | Selective silicon-on-insulator isolation structure and method A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into ... | 02/05/2008 |
| 7326984 | MIS capacitor and method of formation An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a ni... | 02/05/2008 |
| 7326975 | Buried channel type transistor having a trench gate and method of manufacturing the same In a method of manufacturing a buried channel type transistor, a trench is formed at a surface portion of a substrate. A first and a second threshold voltage control regions are formed at portions of the substrate beneath a bottom face of the trench and adjacent to ... | 02/05/2008 |
| 7326611 | DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arrays The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars... | 02/05/2008 |
| 7327007 | Semiconductor device with high breakdown voltage A technique is provided which allows easy achievement of a semiconductor device with desired breakdown voltage. In a high-potential island region defined by a p impurity region, an n+ impurity region is formed in an n− semiconductor layer, an... | 02/05/2008 |
| 7326995 | Trench MIS device having implanted drain-drift region and thick bottom oxide A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. T... | 02/05/2008 |
| 7327011 | Multi-surfaced plate-to-plate capacitor and method of forming same A plate to plate capacitor has a first plate, a second plate, and an insulating medium separating the first plate from the second plate. The first plate and the second plate are adapted and arranged to form an interlaced structure in which multiple capacitance surfa... | 02/05/2008 |
| 7326990 | Semiconductor device and method for fabricating the same A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least on... | 02/05/2008 |
| 7326987 | Non-continuous encapsulation layer for MIM capacitor The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Lin... | 02/05/2008 |
| 7326993 | Nonvolatile semiconductor memory and method for fabricating the same A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first sem... | 02/05/2008 |
| 7326985 | Method for fabricating metallic bit-line contacts A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between th... | 02/05/2008 |
| 7323708 | Phase change memory devices having phase change area in porous dielectric layer A phase change memory device includes a lower electrode and a porous dielectric layer having fine pores on the lower electrode. A phase change layer is provided in the fine pores of the porous dielectric layer. An upper electrode is provided on the phase change laye... | 01/29/2008 |
| 7323734 | Phase changeable memory cells A phase changeable memory cell is disclosed. According to embodiments of the invention, a phase changeable memory cell is formed that has a reduced contact area with one of the electrodes, compared to previously known phase changeable memory cells. This contact area... | 01/29/2008 |
| 7323735 | Method of manufacturing semiconductor integrated circuit device having capacitor element In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) ... | 01/29/2008 |
| 7324396 | Sense amplifier organization for twin cell memory devices A semiconductor memory device is provided that uses a single wordline to access both storage cells of a so-called twin cell. A memory device comprises a plurality of wordlines and a plurality of bitlines in an array, with a plurality of storage cells at certain inte... | 01/29/2008 |
| 7324367 | Memory cell and method for forming the same A semiconductor memory cell structure having 4 F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the su... | 01/29/2008 |
| 7324366 | Non-volatile memory architecture employing bipolar programmable resistance storage elements A nonvolatile memory array includes a plurality of word lines, a plurality of bit lines, a plurality of source lines, and a plurality of nonvolatile memory cells. Each of at least a subset of the plurality of memory cells has a first terminal connected to one of the... | 01/29/2008 |
| 7323387 | Method to make nano structure below 25 nanometer with high uniformity on large scale A method of making a nano structure smaller than 25 nanometers utilizing atomic layer deposition, planarizing, and etching techniques. ... | 01/29/2008 |
