Bizarre Patents
Method and apparatus for making a drink hop along a bar or counter
A method for generating a drink which appears to hop from a remote spot on the bar or counter and take one or more leaps, before landing in a patron's glass.
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| Number | Title | Issue Date |
| 8188526 | Semiconductor device It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention ... | 05/29/2012 |
| 8169012 | Semiconductor device and method of fabricating the semiconductor device A semiconductor device and a method of fabricating a semiconductor device provide high quality cylindrical capacitors. The semiconductor device includes a substrate defining a cell region and a peripheral circuit region, a plurality of capacitors in the cell region,... | 05/01/2012 |
| 8164129 | Semiconductor device enabling further microfabrication A semiconductor device includes a plurality of MOS transistors and wiring connected to a source electrode or a drain electrode of the plurality of MOS transistors and, the wiring being provided in the same layer as the source electrode and the drain electrode in a s... | 04/24/2012 |
| 8159013 | Semiconductor integrated circuit device having a dummy metal wiring line There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC proce... | 04/17/2012 |
| 8159012 | Semiconductor device including insulating layer of cubic system or tetragonal system Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in ... | 04/17/2012 |
| 8148763 | Three-dimensional semiconductor devices Provided are a three-dimensional semiconductor device and a method of operating the same. The three-dimensional semiconductor device includes: a plurality of word line structures on a substrate; active semiconductor patterns between the plurality of word line struct... | 04/03/2012 |
| 8138537 | Semiconductor device with grooved capacitor structure In a semiconductor device comprising a capacitive element, an area of the capacitive element is reduced without impairing performance, and further, without addition of an extra step in a manufacturing process. A first capacitor is formed between an active region of ... | 03/20/2012 |
| 8138536 | Semiconductor device having cylindrical lower electrode of capacitor and manufacturing method thereof To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; a... | 03/20/2012 |
| 8134194 | Memory cells, memory cell constructions, and memory cell programming methods Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component ... | 03/13/2012 |
| 8129770 | Semiconductor device and manufacturing method thereof A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the g... | 03/06/2012 |
| 8129768 | Integrated circuit device, manufacturing method thereof, and display device An integrated circuit device of the present invention includes a substrate on which at least two types of nano wire element are provided. These nano wire elements have functions and materials different from each other. The nano wire elements are constituted by nano ... | 03/06/2012 |
| 8129769 | Semiconductor device and manufacturing method thereof A semiconductor device having a 6F2 memory cell whose size is defined by a numerical value of a design rule F, wherein: lower electrodes of capacitors included in the memory cell are supported by a support film; the support film is formed as a pattern com... | 03/06/2012 |
| 8110861 | MIM capacitor high-k dielectric for increased capacitance density According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a high-k dielectric layer comprising AlNX ... | 02/07/2012 |
| 8106435 | Method of forming a semiconductor device having an etch stop layer and related device In one embodiment, a lower interlayer dielectric layer, and first and second landing pads penetrating the lower interlayer dielectric layer are formed on a substrate. Interconnection patterns covering the second landing pads are formed on the lower interlayer dielec... | 01/31/2012 |
| 8097910 | Vertical transistors The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the s... | 01/17/2012 |
| 8093637 | MIM capacitor and associated production method An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor elect... | 01/10/2012 |
| 8093639 | Method for fabricating a semiconductor device An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is form... | 01/10/2012 |
| 8093638 | Systems with a gate dielectric having multiple lanthanide oxide layers Electronic systems and methods of forming the electronic systems include a gate dielectric having multiple lanthanide oxide layers. Such electronic systems may be used in a variety of electronic system applications. A dielectric film having a layer of a lanthanide o... | 01/10/2012 |
| 8084802 | Nonvolatile semiconductor memory A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above... | 12/27/2011 |
| 8084801 | Cell structure for a semiconductor memory device and method of fabricating the same In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on th... | 12/27/2011 |
| 8084800 | Semiconductor device and a method of manufacturing the same In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. T... | 12/27/2011 |
| 8084799 | Integrated circuit with memory having a step-like programming characteristic A memory cell includes a first electrode, a second electrode, and phase change material between the first electrode and the second electrode. The phase change material has a step-like programming characteristic. The first electrode, the second electrode, and the pha... | 12/27/2011 |
| 8058679 | Semiconductor device and semiconductor device manufacturing method A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region forme... | 11/15/2011 |
| 8058678 | Semiconductor memory device including a cylinder type storage node and a method of fabricating the same Provided is a semiconductor memory device including cylinder type storage nodes and a method of fabricating the semiconductor memory device. The semiconductor memory device includes: a semiconductor substrate including switching devices; a recessed insulating layer ... | 11/15/2011 |
| 8053822 | Capacitorless DRAM and methods of manufacturing and operating the same Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrat... | 11/08/2011 |
| 8049259 | Semiconductor device including memory cell having charge accumulation layer A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element region... | 11/01/2011 |
| 8049258 | Disposable pillars for contact formation Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between ... | 11/01/2011 |
| 8044448 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device includes: a memory cell array region having memory cells connected in series; a control circuit region disposed below the memory cell array region; and an interconnection portion electrically connecting the control circuit r... | 10/25/2011 |
| 8035147 | Semiconductor device A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junctio... | 10/11/2011 |
| 8026542 | Low resistance peripheral local interconnect contacts with selective wet strip of titanium Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided. ... | 09/27/2011 |
| 8026543 | Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material patter... | 09/27/2011 |
| 8022455 | Method of fabricating semiconductor device for reducing parasitic capacitance between bit lines and semiconductor device fabricated thereby In a method of fabricating a semiconductor device capable of reducing parasitic capacitance between bit lines and a semiconductor device fabricated by the method, the semiconductor device includes a semiconductor substrate having buried contact landing pads and dire... | 09/20/2011 |
| 8013374 | Semiconductor memory devices including offset bit lines A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality... | 09/06/2011 |
| 8013373 | Semiconductor device having MOS-transistor formed on semiconductor substrate and method for manufacturing thereof A semiconductor device comprises MOS transistors sequentially arranged in the plane direction of a substrate, wherein a gate electrode and a wiring portion for connecting between the gate electrodes to each other are implanted into a layer that is lower than a surfa... | 09/06/2011 |
| 8013375 | Semiconductor memory devices including diagonal bit lines A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and... | 09/06/2011 |
| 8013376 | Memory arrays, semiconductor constructions and electronic systems with transistor gates extending partially over SOI and unit cells within active region pedestals Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in... | 09/06/2011 |
| 8013371 | Ultra thin TCS (SiCl) cell nitride for DRAM capacitor with DCS (SiHCl) interface seeding layer A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride see... | 09/06/2011 |
| 8013372 | Integrated circuit including a stressed dielectric layer with stable stress A method for fabricating an integrated circuit is provided. The method includes providing a substrate having an active region and an opening in the substrate adjacent to the active region. The opening is filled with a dielectric material so as to provide an isolatio... | 09/06/2011 |
| 8008699 | Semiconductor device with circuit for reduced parasitic inductance Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high sid... | 08/30/2011 |
| 8008698 | Semiconductor memory devices having vertical channel transistors and related methods A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with r... | 08/30/2011 |
