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| Number | Title | Issue Date |
| 8183610 | Nonvolatile memory and manufacturing method thereof According to an aspect of the present invention, there is provided a nonvolatile memory including: a cell transistor including: a gate electrode and first and second diffusion layers; a second insulating film covering the cell transistor; first and second plugs pene... | 05/22/2012 |
| 8183611 | Spin transistor using N-type and P-type double carrier supply layer structure A spin transistor that includes: a semiconductor substrate including an upper cladding layer and a lower cladding layer, and a channel layer interposed between the upper and lower cladding layers; a ferromagnetic source and a ferromagnetic drain formed on the semico... | 05/22/2012 |
| 8164128 | Magnetic devices and techniques for formation thereof Techniques for forming a magnetic device are provided. In one aspect, a magnetic device includes a magnetic tunnel junction and a dielectric layer formed over at least a portion of the magnetic tunnel junction. The dielectric layer is configured to have an underlaye... | 04/24/2012 |
| 8134193 | Magneto-resistance effect element and magnetic memory It is possible to reduce a current required for spin injection writing. A magneto-resistance effect element includes: a first magnetization pinned layer; a magnetization free layer; a tunnel barrier layer; a second magnetization pinned layer whose direction of magne... | 03/13/2012 |
| 8129766 | Semiconductor memory device comprising shifted contact plugs A memory includes first contact plugs; ferroelectric capacitors above the first contact plugs; second contact plugs in a first interlayer film being below an area which is between two adjacent ferroelectric capacitors, the second contact plug; first interconnections... | 03/06/2012 |
| 8129767 | Ferroelectric polymer memory module Ferroelectric polymer memory modules are described. In an example, a module has a first set of layers including a first ILD layer defining trenches therein, a first electrode layer disposed in the trenches of the first ILD layer, a first conductive polymer layer dis... | 03/06/2012 |
| 8125011 | Vertical cell edge junction magnetoelectronic device family Magnetoelectronic devices are fabricated by joining the edge of one ferromagnetic thin film element with the top, or bottom, portion of a second ferromagnetic, or nonmagnetic, thin film element. The devices also employ a new operational geometry in which the transpo... | 02/28/2012 |
| 8125010 | Semiconductor device A semiconductor device is proposed in which signal delay due to compensation capacitance elements in peripheral circuit element regions is eliminated. The semiconductor device includes: a first region including memory cells; a second region 10 including a fun... | 02/28/2012 |
| 8120082 | Ferroelectric memory device and method for manufacturing the same Disclosed relates to a ferroelectric memory device that is manufactured easily, operates at low voltage and has excellent data preservation period, and a method of manufacturing the same. In the present invention, a ferroelectric layer 60 is formed on a part ... | 02/21/2012 |
| 8120083 | Polymer-based ferroelectric memory Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode structures separated by a gap; and a polymer-based ferroelectric layer overlying and directly abutting some of t... | 02/21/2012 |
| 8106434 | Semiconductor device with a superparaelectric gate insulator A semiconductor device includes a channel region 18 of semiconductor, a conductive gate electrode 12 adjacent to the channel region 18 and a gate dielectric 10 between the conductive gate electrode 12 and the channel region 18 | 01/31/2012 |
| 8101983 | Nonvolatile memory device comprising one switching device and one resistant material and method of manufacturing the same A nonvolatile memory device including one transistor and one resistant material and a method of manufacturing the nonvolatile memory device are provided. The nonvolatile memory device includes a substrate, a transistor formed on the substrate, and a data storage uni... | 01/24/2012 |
| 8101984 | Spin injector A spin injector for use in a microelectronic device such as a field effect transistor (FET) is disclosed. The spin injector includes an array of ferromagnetic elements disposed within a semiconductor. The ferromagnetic elements within the array are arranged and spac... | 01/24/2012 |
| 8101982 | Memory device which comprises a multi-layer capacitor A memory device is provided. The memory device including memory cells having at least three stacked electrodes spaced apart pairwise by dielectric material so that the pairs of electrodes form respective capacitor layers. The capacitors are connected electrically in... | 01/24/2012 |
| 8097909 | Field-effect transistor with spin-dependent transmission characteristics and non-volatile memory using the same When a gate voltage is applied, the Schottky barrier width due to the metallic spin band in the ferromagnetic source decreasing, up-spin electrons from the metallic spin band are tunnel-injected into the channel region. However, down-spin electrons from the nonmagne... | 01/17/2012 |
| 8089111 | Switchable two terminal multi-layer perovskite thin film resistive device and methods thereof A switchable resistive device has a multi-layer thin film structure interposed between an upper conductive electrode and a lower conductive electrode. The multi-layer thin film structure comprises a perovskite layer with one buffer layer on one side of the perovskit... | 01/03/2012 |
| 8089112 | Semiconductor device and manufacturing method thereof The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment... | 01/03/2012 |
| 8089110 | Switchable memory diodes based on ferroelectric/conjugated polymer heterostructures and/or their composites An embodiment of the present memory cell includes a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjug... | 01/03/2012 |
| 8080841 | Semiconductor device having a ferroelectric capacitor and method of manufacturing the same A semiconductor device includes a semiconductor substrate, a plurality of transistors connected in series and including a transistor having first and second diffusion regions arranged in the semiconductor substrate. The device also includes an insulating film column... | 12/20/2011 |
| 8076706 | Ferroelectric memory device and method of manufacturing the same A ferroelectric memory device includes: a substrate; a first insulating film formed above the substrate, the first insulating film including a plug; a ferroelectric capacitor formed above the first insulating film; the ferroelectric capacitor including a lower elect... | 12/13/2011 |
| 8076705 | Capacitor device providing sufficient reliability A capacitor device includes a dielectric layer configured to have a composition represented as (Ba1−x, Srx)Ti1−zScyO3+δ (0 | 12/13/2011 |
| 8072016 | EPI substrate with low doped EPI layer and high doped Si substrate layer for media growth on EPI and low contact resistance to back-side substrate The fabrication of seek-scan probe (SSP) memory devices involves processing on both-sides of a wafer. However, there are temperature restrictions on the mover circuitry side of the wafer and doping level constrains for either side of wafer. Using a low doped EPI lay... | 12/06/2011 |
| 8058676 | Spin transistor using double carrier supply layer structure A spin transistor includes a semiconductor substrate including a channel layer having a 2-dimensional electron gas structure and upper and lower cladding layers disposed respectively in upper and lower sides of the channel layer; ferromagnetic source and drain elect... | 11/15/2011 |
| 8058677 | Stress buffer layer for ferroelectric random access memory An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes provid... | 11/15/2011 |
| 8044447 | Semiconductor device and method for manufacturing the same There is provided a semiconductor device including a silicon substrate, a source/drain region formed in a surface layer of the silicon substrate, a first insulating film provided with a first hole on the first source/drain region, a conductive film formed on an inne... | 10/25/2011 |
| 8039884 | Semiconductor device having a contact hole with a curved cross-section and its manufacturing method A semiconductor device includes: a ferroelectric capacitor including a first electrode provided above a substrate, a ferroelectric film provided on the first electrode and a second electrode provided on the ferroelectric film; a hydrogen barrier film that covers a t... | 10/18/2011 |
| 8039885 | MRAM with storage layer and super-paramagnetic sensing layer An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substan... | 10/18/2011 |
| 8035146 | Nonvolatile ferroelectric memory device A nonvolatile ferroelectric memory device includes a plurality of unit cell arrays, wherein each of the plurality of unit cell arrays includes: a bottom word line; a plurality of insulating layers formed on the bottom word line, respectively; a floating channel laye... | 10/11/2011 |
| 8035145 | Magnetic memory device A magnetic memory device is provided. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and... | 10/11/2011 |
| 8030695 | Structure and manufacturing method of semiconductor memory device A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper ... | 10/04/2011 |
| 8030694 | Dielectric film and semiconductor device using dielectric film including hafnium, aluminum or silicon, nitrogen, and oxygen The present invention provides a dielectric film having a high permittivity and a high heat resistance. An embodiment of the present invention is a dielectric film (103) including a composite oxynitride containing an element A made of Hf, an element B made of... | 10/04/2011 |
| 8022454 | Ferroelectric thin films Ferroelectric structures and methods of making the structures are presented. The ferroelectric structures can include an electrode in contact with a ferroelectric thin film. The contact can be arranged so that a portion of the atoms of the ferroelectric thin film ar... | 09/20/2011 |
| 8004029 | Spin transistor, programmable logic circuit, and magnetic memory A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the fir... | 08/23/2011 |
| 7994555 | Spin transistor using perpendicular magnetization A spin transistor useful for device miniaturization and high-density integration is provided. The spin transistor includes: a semiconductor substrate including a channel layer; ferromagnetic source and drain disposed on the semiconductor substrate to be separated fr... | 08/09/2011 |
| 7989862 | Semiconductor device and its manufacturing method A semiconductor device is equipped with a plug conductive layer formed in an interlayer dielectric film on a substrate, and a conductive member provided on the plug conductive layer. The semiconductor device further includes a spacer dielectric film formed on the in... | 08/02/2011 |
| 7985994 | Flux-closed STRAM with electronically reflective insulative spacer Flux-closed spin-transfer torque memory having a specular insulative spacer is disclosed. A flux-closed spin-transfer torque memory unit includes a multilayer free magnetic element including a first free magnetic layer anti-ferromagnetically coupled to a second free... | 07/26/2011 |
| 7982252 | Dual-gate non-volatile ferroelectric memory A dual-gate non-volatile memory cell includes a first dielectric layer extending over a first gate, a semiconductor region extending over the first dielectric layer, a second dielectric layer comprising tunnel oxide extending over the semiconductor region, a ferroel... | 07/19/2011 |
| 7977720 | Ferroelectric memory and its manufacturing method To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors ... | 07/12/2011 |
| 7977719 | Magneto-resistance effect element and magnetic memory It is possible to reduce a current required for spin injection writing. A magneto-resistance effect element includes: a first magnetization pinned layer; a magnetization free layer; a tunnel barrier layer; a second magnetization pinned layer whose direction of magne... | 07/12/2011 |
| 7973349 | Magnetic device having multilayered free ferromagnetic layer Magnetic multilayer structures, such as magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves, having a magnetic biasing layer formed next to and magnetically coupled to the free ferromagnetic layer to achieve a desired stability against fluctuations ... | 07/05/2011 |
