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| Number | Title | Issue Date |
| 7994550 | Semiconductor structures having both elemental and compound semiconductor devices on a common substrate A semiconductor structure comprising: a substrate; a seed layer supported by the substrate; an elemental semiconductor layer disposed over a first portion of the seed layer; and a compound semiconductor layer disposed on a second portion of the seed layer. The first... | 08/09/2011 |
| 7943974 | Spin MOS field effect transistor and tunneling magnetoresistive effect element using stack having Heusler alloy A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region ... | 05/17/2011 |
| 7888713 | Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate including a compound semiconductor, a semiconductor layer formed on a surface of the substrate and a constituent of the semiconductor layer including a nitride semiconductor different from a constituent of the substrate, a... | 02/15/2011 |
| 7875914 | Switch mode power amplifier using mis-HEMT with field plate extension Disclosed are a switch mode power amplifier and a field effect transistor especially suitable for use in a switch mode power amplifier. The transistor is preferably a compound high electron mobility transistor (HEMT) having a source terminal and a drain terminal wit... | 01/25/2011 |
| 7859030 | Heterojunction bipolar transistor and fabrication method of the same A SiGe-HBT having a base region made of SiGe mixed crystal. The base region includes: an intrinsic base region having junctions with a collector region and an emitter region; and an external base region for connecting the intrinsic base region with a base electrode.... | 12/28/2010 |
| 7709867 | Spin MOS field effect transistor and tunneling magnetoresistive effect element using stack having Heusler alloy A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region ... | 05/04/2010 |
| 7683406 | Semiconductor device and method for forming the same The present invention is related to semiconductor device and method for manufacturing the same. In accordance with the semiconductor device and method for manufacturing the same, at least one opening extending between LDD regions and exposing a buried insulating lay... | 03/23/2010 |
| 7491988 | Transistors with increased mobility in the channel zone and method of fabrication A semiconductor transistor structure with increased mobility in the channel zone and a method of its fabrication are described. A semiconductor substrate having a first dopant is formed. A diffusion barrier layer having a second dopant is formed on the semiconductor... | 02/17/2009 |
| 7432542 | Semiconductor device with electrostrictive layer in semiconductor layer and method of manufacturing the same A semiconductor device includes a first semiconductor layer, and a first insulated-gate field-effect transistor of a first conductivity type that is provided in a major surface region of the first semiconductor layer. The semiconductor device further includes an ele... | 10/07/2008 |
| 7432541 | Metal oxide semiconductor field effect transistor A metal oxide semiconductor field effect transistor (MOSFET) is disclosed. The MOSFET includes a semiconductor substrate, a germanium layer formed by implanting germanium (Ge) ions into the semiconductor substrate, an epitaxial layer doped with high concentration im... | 10/07/2008 |
| 7422953 | Semiconductor device and method of manufacturing the same There is provided a method of manufacturing a semiconductor device, including forming a structure including a first layer containing Si and a metal oxide layer in contact with the first layer, the metal oxide layer having a dielectric constant higher than that of si... | 09/09/2008 |
| 7420261 | Bulk nitride mono-crystal including substrate for epitaxy The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to... | 09/02/2008 |
| 7417271 | Electrode structure having at least two oxide layers and non-volatile memory device having the same An electrode structure having at least two oxide layers that more reliably switch and operate without the use of additional devices and a non-volatile memory device having the same are provided. The electrode structure may include a lower electrode, a first oxide la... | 08/26/2008 |
| 7368510 | Organic semiconductor copolymers containing oligothiophene and n-type heteroaromatic units An exemplary organic semiconductor copolymer includes a polymeric repeat structure having a polythiophene structure and an electron accepting unit. The electron accepting unit has at least one electron-accepting heteroaromatic structure with at least one electron-wi... | 05/06/2008 |
| 7351951 | Optoelectronic semiconductor device and method of manufacturing such a device The invention relates to a semiconductor device (10) comprising a semiconductor element (1), particularly a solid-state image sensor (1), comprising a semiconductor body (11) of which one surface comprises an optically active part (1 | 04/01/2008 |
| 7320917 | Semiconductor device and method for manufacturing the same Gate length is 110 nm±15 nm or shorter (130 nm or shorter in a design rule) or an aspect ratio of an area between adjacent gate electrode structures thereof (ratio of the height of the gate electrode structure to the distance between the gate electrode structures) ... | 01/22/2008 |
| 7304336 | FinFET structure and method to make the same A multiple-gate FET structure includes a semiconductor substrate. A gate region is formed on the semiconductor substrate. The gate region comprises a gate portion and a channel portion. The gate portion has at least two opposite vertical surfaces adjacent to the cha... | 12/04/2007 |
| 7256465 | Ultra-shallow metal oxide surface channel MOS transistor An ultra-shallow surface channel MOS transistor and method for fabricating the same have been provided. The method comprises: forming CMOS source and drain regions, and an intervening well region; depositing a surface channel on the surface overlying the well region... | 08/14/2007 |
| 7242041 | Field-effect transistors with weakly coupled layered inorganic semiconductors A field-effect transistor includes source, drain, and gate electrodes; a crystalline or polycrystalline layer of inorganic semiconductor; and a dielectric layer. The layer of inorganic semiconductor has an active channel portion physically extending from the source ... | 07/10/2007 |
| 7242049 | Memory device A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the... | 07/10/2007 |
| 7227239 | Resettable fuse device and method of fabricating the same A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension regio... | 06/05/2007 |
| 7221007 | Sheet for optical-semiconductor element encapsulation and process for producing optical semiconductor device using the sheet The invention provides a sheet for optical-semiconductor element encapsulation, which has a multilayer structure including at least two resin layers. The at least two resin layers include: (A) an outermost resin layer (layer A) that is to be brought into contact wit... | 05/22/2007 |
| 7214632 | Using selective deposition to form phase-change memory cells A phase-change memory cell may be formed by selectively depositing the lower electrode in the phase-change memory pore. Thereafter, an adhesion-promoting material may be selectively deposited on the selectively deposited lower electrode and the upper surface surroun... | 05/08/2007 |
| 7202517 | Multiple gate semiconductor device and method for forming same A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device. ... | 04/10/2007 |
| 7196929 | Method for operating a memory device having an amorphous silicon carbide gate insulator A floating gate transistor has a reduced barrier energy at an interface with an adjacent amorphous silicon carbide (a-SiC) gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The... | 03/27/2007 |
| 7193255 | Semiconductor device with floating conducting region placed between device elements Floating conducting regions at floating potentials are placed on a substrate surface between adjacent conducting regions to which predetermined potentials are applied. This makes it possible to block the spread of a depletion layer to the substrate between the condu... | 03/20/2007 |
| 7183567 | Using selective deposition to form phase-change memory cells A phase-change memory cell may be formed by selectively depositing the lower electrode in the phase-change memory pore. Thereafter, an adhesion-promoting material may be selectively deposited on the selectively deposited lower electrode and the upper surface surroun... | 02/27/2007 |
| 7180109 | Field effect transistor and method of fabrication The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then f... | 02/20/2007 |
| 7169666 | Method of forming a device having a gate with a selected electron affinity A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the... | 01/30/2007 |
| 7154153 | Memory device A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the... | 12/26/2006 |
| 7141856 | Multi-structured Si-fin Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produc... | 11/28/2006 |
| 7132714 | Vertical carbon nanotube-field effect transistor and method of manufacturing the same Provided are a vertical carbon nanotube field effect transistor (CNTFET) and a method of manufacturing the same. The method includes: forming a first electrode on a substrate; forming a stack of multiple layers (“multi-layer stack”) on the first electrode, the m... | 11/07/2006 |
| 7132730 | Bulk nitride mono-crystal including substrate for epitaxy The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to... | 11/07/2006 |
| 7129550 | Fin-shaped semiconductor device A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area between gate electrodes ea... | 10/31/2006 |
| 7118970 | Methods of fabricating silicon carbide devices with hybrid well regions MOS channel devices and methods of fabricating such devices having a hybrid channel are provided. Exemplary devices include vertical power MOSFETs that include a hybrid well region of silicon carbide and methods of fabricating such devices are provided. The hybrid w... | 10/10/2006 |
| 7109548 | Operating a memory device A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the... | 09/19/2006 |
| 7105895 | Epitaxial SiObarrier/insulation layer A method for producing an insulating or barrier layer (FIG. 1B), useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on a silicon substrate whereby said deposited layer is substantially free of defects... | 09/12/2006 |
| 7087471 | Locally thinned fins In a FinFET integrated circuit, the fins are formed with a reduced body thickness in the body area and then thickened in the S/D area outside the body to improve conductivity. The thickening is performed with epitaxial deposition while the lower portion of the gates... | 08/08/2006 |
| 7084442 | Double gate transistor arrangement for receiving electrical signals from living cells The invention involves an array to couple a live cell, in particular a nerve cell, with an electronic circuit to pick up directly or indirectly electrically active cell signals and/or to electronically stimulate the cell, where the coupling array comprises a transis... | 08/01/2006 |
| 7074643 | Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices are provided by successively etching a mask layer to provide windows for formation of a source region or a first conductivity type, a buried silicon carbide region... | 07/11/2006 |
