Class 257/287 - With multiple channels or channel segments connected in parallel, or with channel much wider than length between source and drain (e.g., power JFET)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter including more than one channel or channel
No. of patents: 207
Last issue date: 01/17/2012

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Number	Title	Issue Date
8097906	Semiconductor device having finger electrodes A semiconductor device which has low input inductance is provided. It includes: source finger electrodes (3) disposed by predetermined direction on the main substrate 1; drain finger electrodes (4) placed and disposed a predetermined inte...	01/17/2012
7902575	Field-effect microelectronic device, capable of forming one or several transistor channels The invention relates to a field-effect microelectronic device, as well as the method of production thereof. The device includes a substrate as well as at least one improved structure capable of forming one or more transistor channels. This structure, formed by a pl...	03/08/2011
7851832	Semiconductor device Electrode placement which applies easy heat dispersion of a semiconductor device with high power density and high exothermic density is provided for the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a...	12/14/2010
7679111	Termination structure for a power semiconductor device A power semiconductor device having a termination structure that includes a polysilicon field plate, a metallic field plate, and a polysilicon equipotential ring. ...	03/16/2010
7667247	Method for passivating gate dielectric films The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, treating the dielectric layer with a carbon containing group, formin...	02/23/2010
7646045	Method for fabricating a nanoelement field effect transistor with surrounded gate structure A nanoelement field effect transistor includes a nanotube disposed on the substrate. A first source/drain region is coupled to a first end portion of the nanoelement and a second source/drain region is coupled to a second end portion of the nanoelement. A recess in ...	01/12/2010
7633102	Low voltage high density trench-gated power device with uniformly doped channel and its edge termination Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant r...	12/15/2009
7586137	Non-volatile memory device and method of fabricating the same A non-volatile memory device having an asymmetric channel structure is provided. The non-volatile memory device includes a semiconductor substrate, a source region and a drain region which are formed in the semiconductor substrate and doped with n-type impurities, a...	09/08/2009
7569875	Semiconductor device and a method for producing the same A semiconductor device having a substrate; an emitter electrode or source electrode formed on the top surface side of the substrate; a gate electrode formed on the top surface side of the substrate; and a collector electrode or drain electrode formed on the bottom s...	08/04/2009
7560756	Tri-gate devices and methods of fabrication The present invention is a semiconductor device comprising a carbon nanotube body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the carbon nanotube body and on the laterally oppos...	07/14/2009
7557394	High-voltage transistor fabrication with trench etching technique A lateral high-voltage depletion-mode device structure in which fingers of semiconductor material are interdigitated with trench gates. Since the effective channel area is proportional to the depth of the trenches, a large amount of active channel area can be achiev...	07/07/2009
7504678	Tri-gate devices and methods of fabrication The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite ...	03/17/2009
7442971	Self-biasing transistor structure and an SRAM cell having less than six transistors By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect tran...	10/28/2008
7427788	Multi bridge channel field effect transistors with nano-wire channels and methods of manufacturing the same A field effect transistor (FET) includes spaced apart source and drain regions disposed on a substrate and at least one pair of elongate channel regions disposed on the substrate and extending in parallel between the source and drain regions. A gate insulating regio...	09/23/2008
7391087	MOS transistor structure and method of fabrication An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or sili...	06/24/2008
7385273	Power semiconductor device A power semiconductor device that includes a plurality of gate structure each having a gate insulation of a first thickness, and a termination region, the termination including a field insulation body surrounding the active region and having a recess that includes a...	06/10/2008
7354831	Multi-channel transistor structure and method of making thereof A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also inclu...	04/08/2008
7329387	Field-effect transistor, sensor using it, and production method thereof A sensor which has high measuring sensitivity and is excellent in response is provided by forming a porous film in a sensitive section of a field-effect transistor. It comprises a porous body, which is formed on a sensitive section (here, a gate insulating film) of ...	02/12/2008
7329913	Nonplanar transistors with metal gate electrodes A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second...	02/12/2008
7326953	Layer sequence for Gunn diode The invention relates to a layered construction for a Gunn diode. The layered construction comprises a series of stacked layers consisting of a first highly doped nd GaAs layer (3), a graded AlGaAs layer (5), which is placed upon the first h...	02/05/2008
7323386	Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region m...	01/29/2008
7321142	Field effect transistor On an SiC single crystal substrate, an electric field relaxation layer and a p− type buffer layer are formed. The electric field relaxation layer is formed between the p− type buffer layer and the SiC single crystal substrate to contact SiC single crystal substr...	01/22/2008
7312481	Reliable high-voltage junction field effect transistor and method of manufacture therefor The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well regio...	12/25/2007
7304347	Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial l...	12/04/2007
7297580	Methods of fabricating transistors having buried p-type layers beneath the source region The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer...	11/20/2007
7288803	III-nitride power semiconductor device with a current sense electrode A III-nitride power semiconductor device that includes a current sense electrode. ...	10/30/2007
7282760	Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconduc...	10/16/2007
7276723	Ultra-linear multi-channel field effect transistor Alternate layers of wide band gap and narrow band gaps of different kinds of semiconductors are used to form multiple channels of a FET. The channels are doped or formed as 2-DEG/2-DHG in narrow band semiconductor by charge supply layer in the wide band gap semicond...	10/02/2007
7274051	Field effect transistor (FET) having wire channels and method of fabricating the same In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, t...	09/25/2007
7268394	JFET structure for integrated circuit and fabrication method Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alte...	09/11/2007
7268046	Dual gate oxide high-voltage semiconductor device and method for forming the same A dual gate oxide high-voltage semiconductor device and method for forming the same are provided. Specifically, a device formed according to the present invention includes a semiconductor substrate, a buried oxide layer formed over the substrate, a silicon layer for...	09/11/2007
7265399	Asymetric layout structures for transistors and methods of fabricating the same High power transistors are provided. The transistors include a source region, a drain region and a gate contact. The gate contact is positioned between the source region and the drain region. First and second ohmic contacts are provided on the source and drain regio...	09/04/2007
7235840	Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconduc...	06/26/2007
7221010	Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on...	05/22/2007
7221551	Cascaded gate-driven ESD clamp A method is provided for semiconductor ESD protection in a mixed voltage device using a cascaded gate driven NMOS clamp circuit. Use of a bias circuit allows for an external I/O signal to have a voltage higher than the internal circuit power supply voltage so that a...	05/22/2007
7211864	Fully-depleted castellated gate MOSFET device and method of manufacture thereof A fully depleted castellated-gate MOSFET device is disclosed along with a method of making the same. The device has robust I/O applications, and includes a semiconductor substrate body having an upper portion with an upper end surface and a lower portion with a lowe...	05/01/2007
7202517	Multiple gate semiconductor device and method for forming same A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device. ...	04/10/2007
7195965	Premature breakdown in submicron device geometries The concept of the present invention describes a semiconductor device with a junction 504 between a lightly doped region 501 and a heavily doped region 502, wherein the junction has an elongated portion 504a and curved portions ...	03/27/2007
7187022	Semiconductor device having a multi-bridge-channel and method for fabricating the same In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in u...	03/06/2007
7166894	Schottky power diode with SiCOI substrate and process for making such diode The present invention relates to a power junction device including a substrate of the SiCOI type with a layer of silicon carbide (16) insulated from a solid carrier (12) by a buried layer of insulant (14), and including at least one Schottky con...	01/23/2007

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Class 257/287 - With multiple channels or channel segments connected in parallel, or with channel much wider than length between source and drain (e.g., power JFET)