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| Number | Title | Issue Date |
| 7948016 | Off-center deposition of organic semiconductor in an organic semiconductor device The present disclosure provides a method of making a thin film semiconductor device such as a transistor comprising the steps of: a) providing a substrate bearing first and second conductive zones which define a channel therebetween, where the channel does not borde... | 05/24/2011 |
| 7880202 | Modulated-Vt transistor A semiconductor field effect transistor can be used with RF signals in an amplifier circuit. The transistor includes a source region and a drain region with a channel region interposed in between the source and drain regions. The transistor is structured such that t... | 02/01/2011 |
| 7772622 | Field effect transistor and manufacturing method thereof A manufacturing method of a field effect transistor in which, a patterned gate electrode is provided on a substrate, and a gate insulator is provided on the substrate and the gate electrode, a source electrode and a drain electrode are spaced apart from each other o... | 08/10/2010 |
| 7646044 | Thin film transistor and thin film transistor array panel A thin film transistor is provided, which includes: a semiconductor layer including an intrinsic portion; a gate electrode overlapping the intrinsic portion; a gate insulating layer disposed between the semiconductor layer and the gate electrode; and source and drai... | 01/12/2010 |
| 7605413 | High voltage devices High voltage devices capable of preventing leakage current caused by inversion layer. In the high voltage device, a substrate comprises an active area formed therein, a source region and a drain region formed in the substrate, and a gate structure is formed on the a... | 10/20/2009 |
| 7417270 | Distributed high voltage JFET A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average do... | 08/26/2008 |
| 7391087 | MOS transistor structure and method of fabrication An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or sili... | 06/24/2008 |
| 7365403 | Semiconductor topography including a thin oxide-nitride stack and method for making the same A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes grow... | 04/29/2008 |
| 7342310 | Multi-chip package with high-speed serial communications between semiconductor die A multi-chip package includes a package substrate. First and second semiconductor die are formed on the package substrate. The first and the second semiconductor die are configured to communicate with each other via a high-speed serial communications protocol. ... | 03/11/2008 |
| 7339242 | NAND-type flash memory devices and fabrication methods thereof In an embodiment, a memory device includes a semiconductor substrate having cell active regions and a peripheral active region. Plugs, including bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interc... | 03/04/2008 |
| 7314804 | Plasma implantation of impurities in junction region recesses A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in j... | 01/01/2008 |
| 7312486 | Stripe board dummy metal for reducing coupling capacitance Dishing is known to be a problem after CMP of dielectric layers in which the distribution of embedded metal is non-uniform. This problem has been solved by populating those areas where the density of embedded metal is low with unconnected regions that, instead of be... | 12/25/2007 |
| 7301234 | Stack type semiconductor package module utilizing solder coated stacking protrusions and method for manufacturing the same The stack type semiconductor package module includes a lower semiconductor package having a main substrate, a chip mounted on the main substrate and electrically connected to the main substrate through a wire. An epoxy molding compound (EMC) is provided on the main ... | 11/27/2007 |
| 7238580 | Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant ... | 07/03/2007 |
| 7229878 | Phototransistor of CMOS image sensor and method for fabricating the same A phototransistor of a CMOS image sensor suitable for decreasing the size of layout, and a method for fabricating the phototransistor are disclosed, in which the phototransistor includes a first conductive type semiconductor substrate; an STI layer on the first cond... | 06/12/2007 |
| 7202528 | Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power... | 04/10/2007 |
| 7170118 | Field effect transistor (FET) device having corrugated structure and method for fabrication thereof Within both a field effect transistor (FET) device and a method for fabricating the field effect transistor (FET) device there is provided: (1) a semiconductor substrate; (2) a gate electrode formed over the semiconductor substrate and covering a channel region with... | 01/30/2007 |
| 7129139 | Methods for selective deposition to improve selectivity Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density compr... | 10/31/2006 |
| 7102203 | Semiconductor device including field-effect transistor A semiconductor device capable of inhibiting a threshold voltage from increase also when employing a gate electrode consisting of a metal is provided. This semiconductor device comprises a pair of source/drain regions lifted up in an elevated structure, a gate insul... | 09/05/2006 |
| 7092288 | Non-volatile memory array with simultaneous write and erase feature A non-volatile transistor memory array has individual cells with a current injector and a non-volatile memory transistor. Injector current gives rise to charged particles that can be stored in the memory transistor by tunneling. When a row of the array is activated ... | 08/15/2006 |
| 7091535 | High voltage device embedded non-volatile memory cell and fabrication method A high voltage PMOS device having an improved breakdown voltage is achieved. An asymmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate and source and drain regions within the substrate on either side and adjacent to the gate... | 08/15/2006 |
| 7061055 | Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same A double-gate field-effect transistor includes a substrate, an insulation film formed on the substrate, source, drain and channel regions formed on the insulation film from a semiconductor crystal layer, and two insulated gate electrodes electrically insulated from ... | 06/13/2006 |
| 7023033 | Lateral junction field-effect transistor A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semi... | 04/04/2006 |
| 6977433 | Multi function package A multi-chip package for a computer disc drive. In a preferred embodiment, the multi-chip package (MCP) includes a first die having a buffer function thereon, such as an SDRAM device, and a second die including a channel function and a controller function thereon. T... | 12/20/2005 |
| 6974333 | High-density connection between multiple circuit boards A high-density connection of multiple circuit boards having overlapping ends arranged in a stack. The metal traces on the stacked circuit boards are electrically connected by contact of the ends of the traces, which ends may be pads. The stacked circuit boards can b... | 12/13/2005 |
| 6952020 | Semiconductor device and manufacturing method thereof A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at l... | 10/04/2005 |
| 6946378 | Methods for fabricating protective structures for bond wires A method for fabricating a protective structure for bond wires of a semiconductor device assembly which includes sequentially fabricating one or more layers of the protective structure. After a first layer is formed, each subsequent layer is superimposed upon, conti... | 09/20/2005 |
| 6946727 | Vertical routing structure A vertical routing structure inside a substrate for connecting a pair of trace lines electrically. The trace lines are positioned on the top and bottom surface of a stack layer. The vertical routing structure includes a conductive rod and two bonding pads. The condu... | 09/20/2005 |
| 6888182 | Thin film transistor, method for manufacturing same, and liquid crystal display device using same A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the ... | 05/03/2005 |
| 6815765 | Semiconductor device with function of modulating gain coefficient and semiconductor integrated circuit including the same A semiconductor device has a structure in which an impurity diffusion region with an impurity concentration lower than an impurity concentration of a source and a drain is formed between the source and drain and a channel below the gate, having an asymmetric shape w... | 11/09/2004 |
| 6777728 | Semiconductor device and complementary semiconductor device A semiconductor device includes a channel layer, a gate electrode formed on the channel layer, a p-type source region formed on a first side of the channel layer, and a p-type drain region formed on a second side of the channel layer. A heavy-hole band and a light-h... | 08/17/2004 |
| 6740911 | α-WO3-gate ISFET devices and method of making the same Disclosed is an ISFET comprising a H+-sensing membrane consisting of RF-sputtering a-WO3. The a-WO3/SiO2-gate ISFET of the present invention is very sensitive in aqueous solution, and particularly in acidic aqueous solutio... | 05/25/2004 |
| 6709936 | Narrow high performance MOSFET device design The present invention provides a narrow/short high performance MOS device structure that includes a rectangular-shaped semiconductor substrate region having a first conductivity type. A region of dielectric material is formed at the center of the substrate region. F... | 03/23/2004 |
| 6611012 | Semiconductor device Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the wh... | 08/26/2003 |
| 6576939 | Semiconductor processing methods, methods of forming electronic components, and transistors In one implementation, first and second layers are formed over a substrate. One of the layers has a higher oxidation rate than the other when exposed to an oxidizing atmosphere. The layers respectively have an exposed outer edge spaced inside of the subst... | 06/10/2003 |
| 6548842 | Field-effect transistor for alleviating short-channel effects An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local su... | 04/15/2003 |
| 6504191 | Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated... | 01/07/2003 |
| 6495891 | Transistor having impurity concentration distribution capable of improving short channel effect A semiconductor device has source and drain regions, a gate insulating film, a gate electrode, and a channel region. The channel region includes a region where carriers move between the source and drain regions. An impurity concentration of the channel re... | 12/17/2002 |
| 6445034 | MOS transistor having first and second channel segments with different widths and lengths In order to enable non-integer current ratios to be produced in current mirror circuits using small transistors the channel area is adjusted by changes in the channel length over part of the width of the channel. In further embodiments the transistor is f... | 09/03/2002 |
| 6373102 | Process for fabricating a channel region of a transistor device with ion implantation and the transistor device formed therefrom The invention is related to a method for fabricating a channel region of a transistor device by ion implantation with a large angle and the transistor device formed therefrom. The transistor device is formed on a substrate. Furthermore, the ion implantati... | 04/16/2002 |
