Class 257/285 - With profiled channel dopant concentration or profiled gate region dopant concentration (e.g., maximum dopant concentration below surface)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein the JFET has a variable impurity
No. of patents: 162
Last issue date: 04/17/2012

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Number	Title	Issue Date
8159008	Method of fabricating a trench-generated transistor structure Trench-generated transistor structures, methods for fabricating transistors using a trench defined in a semiconductor-on-insulator (SOI) wafer, design structures for a trench-generated transistor, and other trench-generated device structures. The source and drain of...	04/17/2012
7968919	Integrated circuit including a charge compensation component A charge compensation component having a drift path between two electrodes, an electrode and a counterelectrode, and methods for producing the same. The drift path has drift zones of a first conduction type and charge compensation zones of a complementary conduction...	06/28/2011
7825441	Junction field effect transistor with a hyperabrupt junction A junction field effect transistor (JFET) has a hyperabrupt junction layer that functions as a channel of a JFET. The hyperabrupt junction layer is formed by two dopant profiles of opposite types such that one dopant concentration profile has a peak concentration de...	11/02/2010
7781809	High voltage depletion layer field effect transistor In a high voltage junction field effect transistor, a first well (11) of a first conductivity type is formed in a substrate (10) of a second conductivity type. A source (14) and a drain (15) which are each of the first conductivity type a...	08/24/2010
7592653	Stress relaxation for top of transistor gate An improved way to apply tensile or compressive stress to one or more transistors on a semiconductor device is described. A portion of the tensile or compressive stress liner may be removed or modified such that a reduced amount of stress, or even no stress, is appl...	09/22/2009
7535041	Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance A method for making a semiconductor device which may include providing a substrate having a plurality of spaced apart superlattices therein, and forming source and drain regions in the substrate defining a channel region therebetween and with the plurality of spaced...	05/19/2009
7525138	JFET device with improved off-state leakage current and method of fabrication A junction field effect transistor comprises a semiconductor substrate. A first impurity region of a first conductivity type is formed in the substrate. A second impurity region of the first conductivity type is formed in the substrate and spaced apart from the firs...	04/28/2009
7453107	Method for applying a stress layer to a semiconductor device and device formed therefrom A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to co...	11/18/2008
7420232	Lateral junction field effect transistor and method of manufacturing the same A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more hea...	09/02/2008
7417270	Distributed high voltage JFET A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average do...	08/26/2008
7391084	LDMOS transistor device, integrated circuit, and fabrication method thereof An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate (10), a gate region (1) including a gate semiconductor layer region (2; 2′; 151) on top of a gate insulation layer region (3; 141), source (4...	06/24/2008
7385249	Transistor structure and integrated circuit A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedur...	06/10/2008
7348589	Low power consumption magnetic memory and magnetic information recording device A highly integrated magnetic memory with low power consumption is provided. A first element portion which has a free layer, a first pinned layer formed in the film thickness direction of the free layer, and an insulation barrier layer formed between the free layer a...	03/25/2008
7304350	Threshold voltage control layer in a semiconductor device A semiconductor device has a well region having a first conductivity type and formed in an upper portion of a semiconductor substrate, a gate insulating film and a gate electrode formed successively on the well region of the semiconductor substrate, a threshold volt...	12/04/2007
7297618	Fully silicided gate electrodes and method of making the same The present invention relates to a method of selectively fabricating metal gate electrodes in one or more device regions by fully siliciding (FUSI) the gate electrode. The selective formation of FUSI enables metal gate electrodes to be fabricated on devices that are...	11/20/2007
7297994	Semiconductor device having a retrograde dopant profile in a channel region An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so t...	11/20/2007
7274056	Semiconductor constructions The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. Th...	09/25/2007
7242040	Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel,...	07/10/2007
7224027	High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an e...	05/29/2007
7211845	Multiple doped channel in a multiple doped gate junction field effect transistor A multiple doped channel in a multiple doped gate junction field effect transistor. In accordance with a first embodiment of the present invention, a junction field effect transistor (JFET) circuit structure comprises a vertical channel. The vertical channel compris...	05/01/2007
7205619	Method of producing semiconductor device and semiconductor device A semiconductor device able to secure electrical effective thicknesses required for insulating films of electronic circuit elements by using depletion of electrodes of the electronic circuit elements even if the physical thicknesses of the insulating films are not d...	04/17/2007
7202528	Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power...	04/10/2007
7187021	Static induction transistor A transistor switch for a system operating at high frequencies is provided. The transistor switch comprises a graded channel region between a source region and a drain region, the graded channel region configured for providing a low resistance to mobile negative cha...	03/06/2007
7180105	Normally off JFET A normally off JFET is formed by the implantation of a P base; and a shallower P island atop the P base, forming a narrow lateral conduction channel between the two and a shallow gate implant in the device top surface which forms a second lateral conduction channel ...	02/20/2007
7173284	Silicon carbide semiconductor device and manufacturing method A silicon carbide semiconductor device that includes J-FETs has a drift layer of epitaxially grown silicon carbide having a lower impurity concentration level than a substrate on which the drift layer is formed. Trenches are formed in the surface of the drift layer,...	02/06/2007
7166890	Superjunction device with improved ruggedness An improved superjunction semiconductor device includes a charged balanced pylon in a body region, where a top of the pylon is large to create slight charge imbalance. A MOSgated structure is formed over the top of the pylon and designed to conduct current through t...	01/23/2007
7157756	Field effect transistor A field-effect transistor includes a channel layer that is formed on a predetermined semiconductor layer and has an impurity concentration varying from a low value to a high value, and a source region and a drain region each having a bottom face above the predetermi...	01/02/2007
7141840	Semiconductor device and production method therefor A semiconductor device having a high degree of reliability is provided. A second object of the invention is to provide a semiconductor device of high yield. The semiconductor includes a silicon substrate, a gate dielectric film formed on one main surface of the sili...	11/28/2006
7135373	Reduction of channel hot carrier effects in transistor devices A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shal...	11/14/2006
7129533	High concentration indium fluorine retrograde wells A method and apparatus to form a high-concentration, indium-fluorine retrograde well within a substrate. The indium-fluorine retrograde well includes an indium concentration greater than about 3E18/cm3. ...	10/31/2006
7119380	Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel,...	10/10/2006
7091535	High voltage device embedded non-volatile memory cell and fabrication method A high voltage PMOS device having an improved breakdown voltage is achieved. An asymmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate and source and drain regions within the substrate on either side and adjacent to the gate...	08/15/2006
7087491	Method and system for vertical DMOS with slots A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the s...	08/08/2006
7083998	Si/SiGe optoelectronic integrated circuits An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum w...	08/01/2006
7067363	Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances and high scaling down density A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel...	06/27/2006
7061746	Semiconductor component with integrated capacitance structure having a plurality of metallization planes A semiconductor component includes an insulating layer, which is configured on a semiconductor substrate and in which a capacitor structure is formed. The capacitor structure has at least two parallel metallization planes, whereby at least one of the planes is confi...	06/13/2006
7049181	Method of making heterojunction P-I-N diode A heterojunction P-I-N diode switch comprises a first layer of doped semiconductor material of a first doping type, a second layer of doped semiconductor material of a second doping type and a substrate on which is disposed the first and second layers. An intrinsic ...	05/23/2006
7049644	Lateral junction field effect transistor and method of manufacturing the same A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more hea...	05/23/2006
7037814	Single mask control of doping levels In an integrated circuit, dopant concentration levels are adjusted by making use of a perforated mask. Doping levels for different regions across an integrated circuit can be differently defined by making use of varying size and spacings to the perforations in the m...	05/02/2006
7038272	Method for forming a channel zone of a transistor and NMOS transistor In a method for forming a channel zone in field-effect transistors, a polysilicon layer is patterned above the channel zone to be formed. The polysilicon layer serves as a mask substrate for the subsequent doping of the channel zone. The expedient patterning of the ...	05/02/2006

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Class 257/285 - With profiled channel dopant concentration or profiled gate region dopant concentration (e.g., maximum dopant concentration below surface)